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N4880A Reference Clock Multiplier

Data Sheets

Verify the Performance of Next-Generation Receivers

The N4880A reference clock multiplier fills a critical requirement for R&D and test engineers who need to characterize and release the next generation of PCI Express main boards, MIPI M-PHY chipsets and SD card UHS-II host devices. With support for multiple reference-clock rates, the multiplier will help you accurately characterize and verify standard compliance under easy-to-reproduce test conditions.

Lock the Stressed-Pattern Generator to the System Reference Clock

In common reference-clock architectures, where the host cannot be driven by an external reference clock, it is necessary to lock the stressed-pattern generator to the same system reference clock used by the receiver under test. Locking the pattern generator to the receiver’s reference clock ensures accurate and reproducible jitter-tolerance test results.

Work with Existing and Emerging Standards

This type of clocking architecture is required by several existing and emerging standards that use an architecture based on a common reference clock:

– PCI Express common reference clock architecture: test of main boards according to the PCI-SIG® card electromechanical specification (CEM)

– MIPI M-PHY: draft specification from the MIPI alliance. Here the N4880A multiplies a low-speed jittered clock from a signal generator to a higher rate jittered clock that can be used directly as the external clock signal for a BERT pattern generator.

– SD UHS-II: draft SD card specification for host devices

Choose from Multiple Clock Rates

The N4880A reference clock multiplier supports all these standards. The N4880A provides a multiplying phase-locked loop (PLL) with a 2 or 5 MHz loop bandwidth. The PLL lets you lock the pattern generator in a Keysight Technologies, Inc. J-BERT N4903B or ParBERT 81250A to the reference clock from the system under test.

You can use the N4880A to multiply to the target data rate directly or you can use clock dividers of the pattern generators. The N4880A enables using J-BERT with its built-in SJ and SSC modulation sources by providing an external clock signal > 6.75 GHz. At its reference clock input, the N4880A supports the following clock rates:

– 100 MHz for PCIe® 1.x, 2.x and 3.0 testing

– 19.2, 26, 38.4 and 52 MHz for MIPI M-PHY devices

– 26 to 52 MHz for SD UHS-II host devices

The bandwidth of the multiplying PLL automatically adapts to the actual clock rate.

Easily Control all Settings

You can control the settings of the N4880A from a stand-alone software running on a Windows PC that is connected to the N4880A with a USB cable.

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