U4305A Protocol Exerciser for PCI Express® 3.0

Overview

• Supports Gen1 (2.5 GT/s), Gen2 (5.0 GT/s), and Gen3 (8.0 GT/s) speeds
• x1, x2, x4, x8, or x16 link widths
• Standard height, half-length card
• Perform thorough link PCIe® Link testing

The Keysight U4305A Exerciser can be configured to provide sub-protocol layer test and debug for legacy and next gener­ation PCIe devices. The U4305A Exerciser for PCIe is an advanced traffic generator that can be used to send and respond to TLP, DLLP, and physical layer packets to stimulate PCIe devices and systems. The Exerciser operates in one of three modes, PCIe, MR-IOV, or SR-IOV. The capabilities of these modes can be enhanced with the purchase of additional software licenses. Specific DUT test case requirements can be written by means of the included API. U4305A is a standard height, half-length PC form factor card as described in the PCI Express specification, and fits into every system including blade servers.

The PCI Express test and debug capabili­ties of the U4305A is broken down into the sub-protocol layers of the specification as shown in Figure 1. By emulating a PCIe component (with or without MRIOV ca­pabilities), the Keysight U4305A Exerciser acts as an ideal link partner by sending appropriate I/O traffic to stimulate the device under test. The device under test can be exercised under various condi­tions and scenarios without influencing the performance parameters of the device under test. The Keysight U4305A Exerciser can send a block of TLP requests of 32 or 64 bit Memory, I/O, Configuration, or Message types as stimulus to the device under test. It can also be used to send completion packets in response to DUT’s requests.

The U4305A PCIe 3.0 Exerciser provides the following:

• Supports Gen1 (2.5 GT/s), Gen2 (5.0 GT/s), and Gen3 (8.0 GT/s) speeds
• Supports LTSSM functions for up to x16 link widths
• Supports simultaneous use of LTSSM and Protocol Exerciser functions
• Provides SR-IOV capabilities at Gen2 speeds
• Provides emulation of non IOV PCIe components, MR-IOV capable component, or SR-IOV capable components
• Emulation of MR-IOV capable components with five virtual hierarchies (with a separate completion queue for each hierarchy)
• Protocol Exerciser GUI provides a graphical control of the U4305A Exerciser card
• API program control can be done through TCL, Python, C++, or C#
• NVMe Emulation of root com­plex or end point provides test and verification tools for device controller initialization and queue management