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What is a Powered Shorts Test?

Figure 1 illustrates connections between two devices for which a powered shorts test would be generated.

Remember that this test is created automatically, and in most cases will work without debug.

Powered Shorts Test

Fig 1 : Powered shorts test checks for shorts between unnailed boundary-scan nodes and any other nailed node

Note that the illustration above does not show actual physical location of the pins. The pin numberings in the illustration are made to fit conventional drawing methodology. For example, the buffers (Figure 2) are conventionally drawn with inputs to the left and outputs to the right. The same goes for the two scan devices which are conventionally drawn to have the TDI/TDO pins at the bottom of the fictitious rectangular package.

Powered Shorts Test

Figure 2 : Conventional drawing of buffers that do not represent physical location of pins

This is done to underscore the importance of providing a complete board_xy file, which contains the xy coordinates of physical location of pins. The test software takes the data provided in your board_xy file to determine the relative adjacencies for each device. The adjacencies identify where shorts can occur with respect to boundary-scan nodes.

Devices u3 and u4 are boundary-scan devices with two nodes, u3_3 and u3_2, connected to a non-scan device, u5. Two input nodes, IN_17 and IN_18, are also connected to u3 and u4.

These pins (u3 pin 1 and u4 pin 24) are physically adjacent to u3 pin 2 and u4 pin 23.
The test software identifies these nodes as potential shorts for this circuit. Because the basic parameters for powered shorts test are an un-nailed boundary-scan node and a nailed node of any other type, InterconnectPlus software would create a powered shorts test for this circuit.

Note that two adjacent pins on device u5, pins 10 and 11, would not be added to the powered shorts test because pin 10 is a disable node that must be held to a constant state during boundary-scan testing. Shorts on this node would be found either during unpowered shorts testing, or during the first phase of interconnect testing.

After you enter your board data, IPG analyzes it and looks for un-nailed boundary-scan nodes. It then examines the X-Y data for powered shorts situations to adjacent nodes. There is an option in the Board Consultant IPG Global Options that determine the radius of the area around the pin in question that will be examined. (Refer to figure 3).

Powered Shorts Test

Figure 3 : One of the options in Board Consultant IPG Global Options that relates to Powered Shorts.

IPG then writes the ITL for the powered shorts test.

When this test is executed, several subtests are run. Each subtest is a cycle through a selected set of nailed nodes connected to multiplexed hybrid drivers. Multiplexing is used to reduce the number of resources needed for the complete test. A detailed diagnostics routine is executed upon failure and results are reported to the print device.

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