Data Sheets
Accurately characterize your multi-gigabit serial interfaces with the 4-tap de-emphasis signal converter N4916B with optional clock multiplier
Key features:
Keysight N4916B Applications
The de-emphasis technique is used in many high-speed serial bus interfaces to compensate for signal distortions caused by the transmission of multi-gigabit electrical signals over PC board traces. With data rates moving beyond 5 Gb/s the simple 2-tap de-emphasis is more and more replaced by 3- or 4-tap de‑emphasis techniques, i.e. for front-side buses such as QPI, PCI Express 3.0 or 12G SAS interfaces, or 10GBASE KR backplanes. The Keysight Technologies, Inc. N4916B de-emphasis signal converter enables R&D and test engineers to accurately emulate transmitter de-emphasis with adjustable 4-tap de-emphasis levels, while being transparent to jitter even on non-balanced pattern streams. It can also be used to compensate for distortions caused by cables, fixtures or testboards in the test set up.
The de-emphasis technique is used in many popular gigabit serial bus interfaces operating at data rates above 1 Gb/s, i.e. PCI Express®, USB3, SATA, 10GBASE-KR, 40GBASE-KR4, QPI, memory buses or Infiniband links.
Analyze error, jitter or eye performance of devices using half-rate clocks
Half-rate clocks are used in some of the highest performance serial bus interfaces, such as front-side buses QPI or memory buses.
By using the N4916B’s clock multiplier (Option 001), an external clock is provided, to use the analyzer of J-BERT N4903B can be used to accurately characterize the error, eye, jitter performance without using a CDR.
Emulating transmitter de‑emphasis
The de-emphasis signal converter N4916B allows emulating a transmitter by varying the de-emphasis in a wide range and for each of the three cursors individually. The N4916B is transparent to jitter on the data and clock signals from the pattern generator. The N4916B outputs are DC coupled, so that even unbalanced pattern streams can be generated without DC drifts.
De-embedding signal degradations
The N4916B can also be used to compensate for some of the signal degradations caused by the test set up; e.g. cables, fixtures, test boards. This is helpful to optimize the jitter budget needed for accurate receiver tolerance characterization.
Analyze BER and eye performance of half-rate clocked devices
The clock multiplier option enables BER measurements using the forwarded half-rate clock to be used as sampling clock for J-BERT N4903B.
Control and programming
The N4916B can be controlled via USB interface from the J-BERT N4903B user interface or from a stand-alone user interface.Programming examples are provided.
×
Please have a salesperson contact me.
*Indicates required field
Thank you.
A sales representative will contact you soon.