DDR Memory Design and Test – A Better Way

Double data rate (DDR) memory is being implemented broadly in computing platforms and embedded applications. The overwhelming concern for developers of these products is interoperability. It starts with the physical layer where the data is transferred on both the rising and falling clock edges, to the functional test of read-to-write timing. You need tools to validate the parametric and protocol aspects of your designs to make sure your design is in compliance, and to see how close design performance is to specification.

When you can gain insight to your design early in the design cycle, you can take corrective action quickly to make sure you meet product quality and time-to market goals. Keysight Technologies, Inc.design and test solutions can provide these insights to help you make the right decisions at key moments.

DDR technology is implemented in several forms today -- DDR (also called DDR1), DDR2, DDR3, DDR4, and low-power DDR (LPDDR1, LPDDR2, and LPDDR3) targeted for mobile devices. Specifications are defined by the Joint Electronic Devices Engineering Council (JEDEC) (see Table 1), but it’s up to you guarantee compliance.

With each advance of DDR, the rising data rates bring new design and test challenges. The higher clock frequencies increase signal integrity symptoms like reflections and crosstalk, causing signal degradation and logic issues. A shorter clock cycle means a smaller jitter budget, so reducing jitter is far more complex. The higher bandwidth requirements need quality probing techniques to ensure the probe isn’t significantly degrading the signal. And lower voltage swings require measurements to be made with very low noise.

Applying expertise

When it comes to quality digital measurements and signal integrity, Keysight has decades of experience in RF and protocol engineering. We understand the reflections, insertion and return loss, jitter budget, timing margins, compliance and other issues that digital designers have to face in high data rate standards. As an active member of JEDEC, with consistent participation in workshops and specification issues, Keysight has a solid background in the physical layer, protocol layer and functional test of DDR memory.

Keysight has a long history of collaborative innovation with industry leaders. It puts Keysight in a position to develop tools that meet the physical challenges, are customized to the needs of the standard, and are relevant to the way designers and developers need to use them.

Complete, reliable test coverage

But what makes Keysight design and test solutions so compelling is that they are the best tools, in every category, to meet the challenges presented by DDR memory. We developed these tools to match the application’s specific needs – real-time and sampling oscilloscopes to verify signal integrity and jitter, probes for low-invasive high accuracy measurements (see Figure 2), pattern/protocol generators to create the necessary stimulus signals, time-domain reflectometer (TDR) and a vector network analyzer (VNA) to characterize impedance, and EDA software to simulate designs.

The quality of Keysight solutions is the key to easier, faster and more confident testing of your DDR designs. Accurate results reduce the number of design cycles to help you get to market faster, and they ensure robust products that uphold your hard-won lead in the market.

Physical Layer: Active Signal Validation

Validating DDR performance involves characterizing the clock signal, and the data read and write signals. For the clock, key parameters are the rising edge, falling edge, and jitter. For data, the challenge is separating the read and write signals on the bidirectional bus to verify the DQ and DQS waveform parameters. The ability to trigger properly will allow you to analyze the complex traffic on the DDR data bus.

Measure with confidence

Whether you are troubleshooting, capturing contiguous waveforms, ensuring correct operation, or proving compliance, an oscilloscope with low noise, low jitter, and high probe accuracy is critical for measurement accuracy. Eye diagram tests examine the minimum eye opening for adequate operation. Separating the read and write signals on the bidirectional data bus requires a sophisticated triggering system to overcome the limitations of simply triggering on the read/write preamble or signal amplitude.

Keysight’s Infiniium 90000 Series oscilloscopes provide the lowest noise floor, jitter noise floor, and trigger jitter in the industry, enabling you to more accurately characterize your design. The InfiniiScan capability provides zone triggering, enabling the oscilloscope to separate read and write cycles based on the distinctive pattern of the waveform (see Figure 3). This is accomplished by drawing zones on the oscilloscope screen to visually determine the event identification condition – whether the waveform intersects or does not intersect the zones.

Automate complex tasks

The Keysight DDR electrical performance compliance and validation software complements the accuracy of the 90000 Series oscilloscopes by simplifying setup and performing compliance tests (see Figure 4). With packages for DDR1, DDR2 and DDR3, the software runs on the oscilloscope itself, using a test framework that has proven value to busy engineers who want quick, accurate answers. The software has the most complete set of DDR tests to evaluate device performance.

The software brings together Keysight’s intimate knowledge of the oscilloscope and careful interpretation of the specifications to ensure the best results, high repeatability with minimal effort. The software produces an HTML report, complete with screenshots, which makes it easy to share your results. It also provides a margin analysis that shows how close your design is to the specification (see Figure 5).