Signal Integrity Simulation of PCI Express Gen 2 Channel

In the electronics industry, there has been an architectural shift over the past several years from parallel bus interfaces to serial communication links. The ben-efits of employing serial links over parallel I/O schemes include fewer device pins, reduced board space requirements, smaller connectors, easier PCB layouts, and less susceptibility to noise. However, there are unique challenges associated with serial link design. The high data rate signals pose challenges previously only familiar to analog RF and microwave designers. Today, many existing serial I/O standards op-erate at multi-Gbps speeds. These standards are evolving, and the next generation versions of the standards aim to increase (or perhaps even double) the data rates achievable in a single lane. For example, PCI Express (PCIe) Gen 1 operates at 2.5 GT/s, while PCIe Gen 2 and PCIe Gen 3 are 5.0 GT/s and 8.0 GT/s, respectively. Fur-ther complicating things is the fact that high-speed serial links often require special data processing, such as SerDes (serializer/deserializer), equalization, and line cod-ing (i.e. 8B10B or 64B66B). For multi-Gbps serial links, a robust approach to signal integrity simulation must be followed in order to avoid costly design iterations.

Figure 1 illustrates a typical link, which consists of driver and receiver ICs, their packages, several connnectors, and PCBs. The passive components of the link are collectively called the channel. To ensure signal integrity, it is crucial to carefully de-sign all aspects of these passive interconnects. At high data rates, it is critical that the channel simulation accurately takes into account the distributed nature and loss mechanisms of the transmission lines, coupling between the traces of differential pairs and any adjacent aggressors/victims, and impedance mismatches. A good practice is to create a virtual prototype of the entire link in a signal integrity EDA (electronic design automation) tool and simulate the eye diagram performance. To illustrate this design flow, a PCIe Gen 2 system, operating at 5 GT/s, is built and simulated in Agilent’s high-frequency/high-speed EDA tool called ADS (Advanced Design System).

Fast Channel Simulation

There is a new, easy to use tool in ADS 2009 called the Channel Simulator. It has huge benefits over traditional SPICE, such as dramatically faster simulation speed and capacity, easy and direct incorporation of S-parameter models, and efficient post processing for large numbers of simulated bits. Further, there is no sacrifice in accuracy in using the Channel Simulator, as long as the channel can be assumed to be an LTI (linear, time-invariant) system. Since all typical interconnects are passive and linear, this is a safe assumption, and classical transient simulation results will overlay perfectly with results from the Channel Simulator. Figure 2 shows a generalized block diagram of systems that can be rapidly analyzed using the Chan-nel Simulator. It supports one transmitter (TX), any number of crosstalk sources (XTLK1, XTLK2, … XTLKN), any arbitrary linear channel model, and a receiver (RX).

The user has great flexibility in choosing the types of components to include in the channel model in ADS. This is an important feature, since signal integrity engineers tend to obtain models in many different formats. For example, connector vendors may supply their customers with S-parameter files, SPICE-equivalent circuit models, or even CAD models that need to be simulated in a 3D electromag-netic (EM) solver. The types of models that can be used to build the virtual channel prototype in ADS include S-parameter files, lumped RLC components, transmission lines, ADS multi-layer library models, HSPICE or Spectre netlists, W-elements, and dynamically-linked electromagnetic models (full 3D or planar). The channel model can even consist of a combination or arbitrary hierarchy of these different model types. When the Channel Simulator is used for a channel that contains models which happen to be constructed in the frequency domain, such as an S-parameter file or certain transmission line models, ADS will automatically invoke the convolu-tion engine to create a casual, passive, and accurate impulse response in the time domain. This allows the user to easily mix time-domain and frequency-domain models.

Figure 3 shows a PCIe Gen 2 channel built in ADS. From left to right (ignoring the resistive and capacitive loads) there are a differential transmitter, package, via breakout, add-in card, connector, system board, via breakout, package, and an Eye Probe. This channel consists of a variety of model types. The via breakout is mod-eled by a single 8 port Touchstone S-parameter file. The 4 inch traces on the add-in card and the 12 inch traces on the system board are all modeled using the multi-layer library in ADS. This library has the advantage of being fully parameterized and therefore easily tunable and optimizable, making it extremely useful for pre-layout “what-if” analysis of transmission lines and vias. For example, the system board and add-in card traces have parameters for length, width, spacing, and layer num-ber. The package is modeled using a combination of coupled transmission lines and an 8 port S-parameter file for the BGA solder balls.

Summary

There are many design considerations for today’s multi-Gbps serial links. Signal integrity designers need to quickly evaluate channel designs in order to make critical trade-offs. Traditional SPICE simulators have too many limitations on speed, capacity, and frequency-domain model support. A PCIe Gen 2 channel was simulated using the Channel Simulator in ADS, which has many advantages over classical SPICE tools. Transmitter de-emphasis and connector model selection were optimized for the channel by using Batch Mode simulations. Electromagnetic simulations of the package