Data Sheets
The 16962A logic analyzer module from Keysight Technologies, Inc. delivers the performance required for high-speed standards and devices like DDR3 and A/D converters. In addition to covering standards, the 16962A provides conventional state and timing measurements on single-ended or differential signals at rates up to 2 GHz. The 100 M samples of memory ensure you capture enough system activity to troubleshoot complex systems.
16962A Logic Analyzer Module
Keysight’s 16962A module provides you with the ability to perform:
Optimized for comprehensive DDR memory analysis
The 16962A logic analysis module with 2.0 GT/s state speed and 2 GHz trigger sequencer speed provides full capability to reliably trigger and capture all DDR activity, including DDR3 2133. When used with a full suite of DDR probing solutions (Interposer, BGA, SODIMM, mid-bus) and compliance/performance analysis software, you obtain full test capability for system integration in the memory industry.
Automate measurement setup and quickly gain diagnostic clues
Quickly get up and running by automating your measurement setup process. In addition, the logic analyzer’s sampling position and threshold voltage settings are automatically determined so that data on high-speed buses is captured with the highest accuracy.
Identify problem signals over hundreds of channels simultaneously
As timing and voltage margins continue to shrink, confidence in signal integrity becomes an increasingly vital requirement in the design validation process. Eye scan lets you acquire signal integrity information on all the buses in your design, under a wide variety of operating conditions, in a matter of minutes. Identify problem signals quickly for further investigation with an oscilloscope. Results can be viewed for each individual signal or as a composite of multiple signals or buses.
Maximize the amount of time captured at high-speed resolution
In timing mode you typically have to sacrifice sampling resolution to acquire more system activity. If your system has bursts of activity followed by times with little activity, you can use transitional timing along with the logic analyzer’s deep memory to capture seconds to minutes of activity at 125 ps (8 GHz) sampling resolution. You also have the flexibility to increase the amount of time captured by excluding certain buses or signals from being stored like clock or strobe signals that add little useful information to the measurement.
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