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HMMC—3022 DC-12 GHz GaAs HBT MMIC Divide-by-2 Prescaler

Data Sheets

Features

  • Wide Frequency Range:

0.2 to 12 GHz

  • High Input Power Sensitivity:

On-chip pre- and post-amps

  • 20 to +10 dBm (1-8 GHz)
  • 15 to +10 dBm (8-10 GHz)
  • 10 to +4 dBm (10-12 GHz)
  • Dual-mode Pout: (chip form)

0 dBm (0.5 Vp-p) @ 40 mA

  • 6.0 dBm (0.25 Vp-p) @ 30 mA
  • Low Phase Noise:
  • 153 dBc/Hz @ 100 kHz Offset
  • (+) or (–) Single Supply Bias operation
  • Wide bias supply range: 4.5 to 6.5 volt operating range
  • Differential I/0 with on-chip 50 Ω matching

Description

The Keysight Technologies, Inc. HMMC-3022 GaAs HBT MMIC Prescaler offers dc to 16 GHz frequency translation for use in communications and EW systems incorporating high-frequency PLL oscillator circuits and signal-path down conversion applications. The prescaler provides a large input power sensitivity window and low phase noise. In addition to the features listed above the device offers an input disable contact pad to eliminate any self-oscillation condition. 

Applications

The HMMC-3022 is designed for use in high frequency communications, microwave instrumentation, and EW radar systems where low phase-noise PLL control circuitry or broadband frequency translation is required.

Operation

The device is designed to operate when driven with either a singleended or differential sinusoidal input signal over a 200 MHz to 16 GHz bandwidth. Below 200 MHz the prescaler input is “slew-rate” limited, requiring fast rising and falling edge speeds to properly divide. The device will operate at frequencies down to dc when driven with a square-wave.

The device may be biased from either a single positive or single negative supply bias. The backside of the device is not dc connected to any dc bias point on the device.

For positive supply operation VCC is nominally biased at any voltage in the +4.5 to +6.5 volt range with VEE (or VEE & VPwrSel) grounded. For negative bias operation VCC is typically grounded and a negative voltage between -4.5 to -6.5 volts is applied to VEE (or VEE & VPwrSel).

Several features are designed into this prescaler:

1. Dual-output power feature

Bonding both VEE and VPwrSel pads to either ground (positive bias mode) or the negative supply (negative bias mode), will deliver ~0 dBm [0.5 Vp-p] at the RF output port while drawing ~40 mA supply current. Eliminating the VPwrSel connection results in reduced output -6.0 dBm [0.25 Vp-p] but at a reduced current draw of ~30 mA resulting in less overall power dissipation.

2. VLogic ECL contact pad

Under normal conditions no connection or external bias is required to this pad and it is self-biased to the on-chip ECL logic threshold voltage (VCC -1.35 V). The user can provide an external bias to this pad (1.5 to 1.2 volts less than VCC) to force the pre-scaler to operate at a system generated logic threshold voltage.

3. Input disable feature

If an RF signal with sufficient signalto- noise ratio is present at the RF input, the prescaler will operate and provide a divided output equal to the input frequency divided by the divide modulus. Under certain “ideal” conditions where the input is well matched at the right input frequency, the device may “self-oscillate,” especially under small signal input powers or with only noise present at the input. This “self-oscillation” will produce an undesired output signal also known as a false trigger. By applying an external bias to the input disable contact pad (more positive than VCC –1.35 V), the input preamplifier stage is locked into either logic “high” or logic “low” preventing frequency division and any self-oscillation frequency which may be present.

4. Input dc offset

Another method used to prevent false triggers or self-oscillation conditions is to apply a 20 to 100 mV dc offset voltage between the RFin and RFin ports. This prevents noise or spurious low level signals from triggering the divider.

Adding a 10 kΩ resistor between the unused RF input to a contact point at the VEE potential will result in an offset of ~25 mV between the RF inputs. Note however, that the input sensitivity will be reduced slightly due to the presence of this offset.

Assembly Techniques

Figure 3 shows the chip assembly diagram for single-ended I/O operation through 12 GHz for either positive or negative bias supply operation. In either case the supply contact to the chip must be capacitively bypassed to provide good input sensitivity and low input power feedthrough. Independent of the bias applied to the device, the backside of the chip should always be connected to both a good RF ground plane and a good thermal heat sinking region on the mounting surface. All RF ports are dc connected on-chip to the VCC contact through on-chip 50 W resistors. Under any bias conditions where VCC is not dc grounded, the RF ports should be ac coupled via series capacitors mounted on the thin-film substrate at each RF port. Only under bias conditions where VCC is dc grounded (as is typical for negative bias supply operation) may the RF ports be direct coupled to adjacent circuitry or in some cases, such as level shifting to subsequent stages. In the latter case the device backside may be “floated” and bias applied as the difference between VCC and VEE.  All bonds between the device and this bypass capacitor should be as short as possible to limit the inductance. For operation at frequencies below 1 GHz, a large value capacitor must be added to provide proper RF bypassing.  Due to on-chip 50 Ω matching resistors at all four RF ports, no external termination is required on any unused RF port. However, improved “Spitback” performance (~20 dB) and input sensitivity can be achieved by terminating the unused RFout port to VCC through 50 Ω (positive supply) or to ground via a 50 Ω termination (negative supply operation). GaAs MMICs are ESD sensitive. ESD preventive measures must be employed in all aspects of storage, handling, and assembly. MMIC ESD precautions, handling considerations, die attach and bonding methods are critical factors in successful GaAs MMIC performance and reliability.

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