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MOI for DisplayPort PHY CTS 1.2b Source Testing
This document is provided "AS IS" and without any warranty of any kind, including, without limitation, any expressed or implied warranty of non-infringement, merchantability or fitness for a particular purpose. In no event shall VESA™ or any member of VESA be liable for any direct, indirect, special, exemplary, punitive, or consequential damages, including, without limitation, lost profits, even if advised of the possibility of such damages. This material is provided for reference only. VESA does not endorse any vendor’s equipment, including equipment outlined in this document.

Application Note 2013-03-21

PDF PDF 5.63 MB
Tips for Making Better Memory Measurements – Video Series
Videos that show customers how perform a comprehensive, unique and extensive analysis in less time.

Demo 2013-03-18

Agilent Technologies Launches Recognition Program for EDA Experts
Agilent launches its Agilent Certified Expert recognition program for EDA experts. Eligible participants include individuals demonstrating a high level of expertise-both theoretical and practical-in applying Agilent EEsof EDA tools for product design and modeling.

Press Materials 2013-03-12

MHL Cable Compliance Test - Test Solution Overview Using the ENA Option TDR
This describes how to make measurements of MHL (Mobile High-definition Link) Cable Compliance Tests by using the Keysight E5071C ENA Option TDR.

Technical Overview 2013-02-22

PDF PDF 2.06 MB
Jitter Measurements on Long Patterns Using 86100DU-401 Advanced Waveform Analysis - Application Note
To overcome pattern length limitations found in many of today’s jitter analysis tools, Keysight developed a Microsoft Office Excel-based application called 86100DU Option 401 Advanced Waveform Analysis

Application Note 2013-02-21

PDF PDF 3.47 MB
Keysight Method of Implementation (MOI) for DisplayPort1.2b Cable-Connector Assembly Compliance Test
Keysight Method of Implementation (MOI) for DisplayPort 1.2b Cable-Connector Assembly Compliance Test Using Keysight E5071C ENA Network Analyzer Option TDR

Application Note 2013-02-18

PDF PDF 1.29 MB
DisplayPort 1.2b Cable-Connector Compliance Test - Test Solution Overview Using the ENA Option TDR
This describes how to make measurements of VESA DisplayPort 1.2b Cable & Connector Compliance Tests by using the Keysight E5071C ENA Option TDR.

Technical Overview 2013-02-18

PDF PDF 2.26 MB
Keysight Method of Implementation (MOI) for MHL Cables Compliance Tests
Keysight Method of Implementation (MOI) for MHL Cable Compliance Tests Using Keysight E5071C ENA Network Analyzer Option TDR

Application Note 2013-02-14

PDF PDF 1.76 MB
Agilent Technologies Commits $90 Million Gift of Software to Georgia Institute of Technology
Agilent announces the largest in-kind software donation ever in its longstanding relationship with the Georgia Institute of Technology.

Press Materials 2013-02-04

Agilent Technologies and SiSoft Introduce Pre-Standard IBIS-AMI Modeling Guide
Agilent and Signal Integrity Software, Inc. (SiSoft) announce guidelines that enable system designers to use advanced jitter and broadband analog capabilities when modeling high-speed serial devices.

Press Materials 2013-01-29

DDR4 TdiVW/VdiVW Bit Error Rate Measurement or Understanding Bit Error Rate
Importance of making BER measurement calculations to form a statistical measurement of total jitter to understand the design's data valid window result and design error rates.

Application Note 2013-01-24

PDF PDF 1.65 MB
USB3.0 Cable-Connector Assembly Compliance Test - Test Solution Overview Using the ENA Option TDR
This describes how to make measurements of USB 3.0 cable & connector assemblies Compliance Tests by using the Keysight E5071C ENA Option TDR.

Technical Overview 2012-12-20

PDF PDF 2.27 MB
DDR Memory Design and Test Overview
Brief overview of Keysight solutions for DDR design and test.

Brochure 2012-12-19

PDF PDF 1.14 MB
DDR Memory Design and Test – A Better Way
Keysight offers the complete solutions for all areas of DDR design, meeting your needs for electrical physical layer, protocol layer, and functional test.

Brochure 2012-12-19

PDF PDF 5.17 MB
Keysight Method of Implementation (MOI) for USB3.0 Cable-Connector Assembly Compliance Test
Keysight Method of Implementation (MOI) for USB3.0 Cable-Connector Assembly Compliance Test Using Keysight E5071C ENA Network Analyzer Option TDR

Application Note 2012-12-17

PDF PDF 1.82 MB
DDR Memory Overview, Development Cycle, and Challenges - Technical Overview
Thanks to improved manufacturing processes that have driven down costs, the technology of choice is now DDR SDRAM, short for Double Data Rate Synchronous Dynamic Random Access Memory.

Application Note 2012-12-14

PDF PDF 1.37 MB
Electrical Redriver Modeling Solution to Solve Key Challenges in Designing Chip-to-Chip Links
Agilent introduces a redriver modeling solution designed to quickly and accurately solve the challenge posed by signal distortion in multigigabit-per-second systems.

Press Materials 2012-11-05

Frequency Domain Analysis of Jitter Amplification in Clock Channels
Clock channel jitter amplification factor in terms of transfer function or S-parameters is derived. Amplification is shown to arise from smaller attenuation in jitter lower sideband than in the fundamental. Amplification scaling with loss is obtained.

Application Note 2012-11-01

PDF PDF 257 KB
Agilent Technologies to Demonstrate High-Speed Digital Design Solutions at EPEPS
Agilent announces it will demonstrate its high-speed digital design solutions at EPEPS 2013, Oct. Oct. 28 & 29, at the DoubleTree by Hilton Hotel in San Jose, Calif

Press Materials 2012-10-28

Keysight Method of Implementation (MOI) for PCI Express 3.0 PCB Differential Trace Impedance Test
Keysight Method of Implementation (MOI) for PCI Express 3.0 PCB Differential Trace Impedance Test Using Keysight E5071C ENA Network Analyzer Option TDR

Application Note 2012-10-16

PDF PDF 1.62 MB
Explore the SERDES Design Space Using the IBIS AMI Channel Simulation Flow
Simulation of modern chip-to-chip links requires you abandon the SPICE-based approach and adopt a new approach based on an IBIS AMI channel simulation flow.

Application Note 2012-09-21

STATS ChipPAC Launches QFN Package Design Kit for Agilent Technologies’ Advanced Design System
STATS ChipPAC announces the launch of its Quad Flat No-Lead (QFN) package design kit for ADS.

Press Materials 2012-09-12

The Power of S-Parameters for High Speed Digital Design Tutorial
Learn to use S-parameters for high-speed digital designs with this video tutorial.

Promotional Materials 2012-09-07

B4623B Bus Decoder for LPDDR, LPDDR2, or LPDDR3 Debug and Validation - Data Sheet
The B4623B protocol-decode software translates Translates acquired signals into easily understood bus transactions showing associated data bursts for LPDDR, LPDDR2, LPDDR3 at full bus data rates.

Data Sheet 2012-09-03

PDF PDF 1.03 MB
Agilent to Demonstrate Test Solutions at International Symposium on Electromagnetic Compatibility
Agilent will demonstrate its test solutions at the IEEE International Symposium on Electromagnetic Compatibility in Pittsburg, Aug. 5-10, 2012.

Press Materials 2012-07-18

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