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Electronic Measurement

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Physical Layer design challenges for PCI Express® 3.0 and 2.0 designs
You will learn advanced techniques for PCI Express phy-layer validation covering the latest PCIe 3.0 specification requirements as well as practical extensions to PCIe 2.0 and 1.1 designs. This seminar analyzes transmitter and receiver performance.

Webcast - recorded

Test and Validation of PCIe/NVMe Protocol Designs Webcast
Live broadcast July 10, 2014; 10am PT/1pm ET/19:00 CET

Webcast - recorded