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Electronic Measurement

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An Innovative Simulation Workflow for Debugging High-Speed Digital Designs Using Jitter Separation
This paper presents a new simulation workflow for jitter separation analysis.

Application Note 2014-08-03

Analysis of Test Coupon Structures for the Extraction of High Frequency PCB Material Properties
Exploration of the addition of Beatty series resonant impedance structures to improve the accuracy of extracting PCB material properties for the purpose of constructing 3D-EM simulations.

Application Note 2014-08-03

PDF PDF 2.19 MB
Simulating High-Speed Serial Channels with IBIS-AMI Models
This paper reviews some of the benefits and limitations of using IBIS models and introduces the new AMI extensions to the latest IBIS version 5.0 specification.

Application Note 2014-08-01

Properly Powering On and Off Multiple Power Inputs in Embedded Designs - Application Not
This is the first in a series of application notes that addresses power optimization, characterization and simulation challenges in embedded designs.

Application Note 2014-07-31

Measuring Jitter in Digital Systems (AN 1448-1) - Application Brief
This application note is for R&D designers and engineers working on high-speed digital designs. It addresses jitter measurements in digital circuits, how the different measurement techniques are best applied, and how these decisions may change as the data rates increase.

Application Note 2013-09-16

PDF PDF 1.78 MB
DDR4 TdiVW/VdiVW Bit Error Rate Measurement or Understanding Bit Error Rate
Importance of making BER measurement calculations to form a statistical measurement of total jitter to understand the design's data valid window result and design error rates.

Application Note 2013-01-24

PDF PDF 1.65 MB
Frequency Domain Analysis of Jitter Amplification in Clock Channels
Clock channel jitter amplification factor in terms of transfer function or S-parameters is derived. Amplification is shown to arise from smaller attenuation in jitter lower sideband than in the fundamental. Amplification scaling with loss is obtained.

Application Note 2012-11-01

PDF PDF 257 KB
Explore the SERDES Design Space Using the IBIS AMI Channel Simulation Flow
Simulation of modern chip-to-chip links requires you abandon the SPICE-based approach and adopt a new approach based on an IBIS AMI channel simulation flow.

Application Note 2012-09-21

Which Electromagnetic Simulator Should I Use?
This paper outlines three of the key EM simulation technologies, MoM, FEM, FDTD and attempt to compare and contrast the relative merits of each.

Application Note 2012-04-06

PDF PDF 3.21 MB
Simulating FPGA Power Integrity Using S-Parameter Models
This application note describes how self-impedance (frequency) can easily be determined by simulating the frequency domain self-impedance profile of a Power Distribution Network (PDN).

Application Note 2012-04-02

S-parameter Series: Using De-embedding Tools for Virtual Probing Application Note
Discusses using de-embedding tools to gain virtual access to difficult measurement points

Application Note 2012-03-11

Effective Reflection Characterization for Active Devices Using ENA Option TDR Application Note
This application note describes Hot TDR measurement, which is an effective characterization method for the reflection of transmitter and receiver.

Application Note 2012-01-12

Understanding the Kramers-Kronig Relation Using A Pictorial Proof
The Kramers-Kronig relation lets us build a causal time-domain model from bandlimited s-parameters. This pictorial proof aids understanding of the physics of causality and hence the validity of this approach.

Application Note 2010-03-31

Using ADS for Signal Integrity Optimization
This white paper shows how to replace a multi-dimensional sweep of a long running PRBS time-domain simulation (including manual data evaluation) by short, channel-pulse characterization in the Advanced Design System to efficiently optimize a channel.

Application Note 2009-10-19

Signal Integrity Analysis Series Part 3: The ABCs of De-Embedding
This Application Note focuses on Part 3: The ABCs of De-Embedding explaining different de-embedding techniques & shows how to minimize fixture effects for best results.

Application Note 2007-07-01

PDF PDF 2.44 MB
Signal Integrity Analysis Series Part 2: 4-Port TDR/VNA/PLTS - Application Note
This Application Note focuses on part 2: those which use a 4-port TDR/VNA/PLTS.

Application Note 2007-02-21

PDF PDF 2.75 MB
Signal Integrity Analysis Series Part 1: Single-Port TDR, TDR/TDT, & 2-Port TDR - Application Note
This Application Note focuses on part 1: those which use a single-port TDR, those which use TDR/TDT, and those which use 2-port TDR.

Application Note 2007-01-01

PDF PDF 3.50 MB
Using Clock Jitter Analysis to Reduce BER in Serial Data Applications
This Application Note emphasizes on the emerging techniques for reference clock jitter analysis from the perspective of oscillator physics, phase noise theory, and serial data technology.

Application Note 2006-12-01

Designing High Speed Backplanes Utilizing Physical Layer Test System
This Application Note focuses on the problems introduced into the backplane assembly design by the many linear passive components that create reflections due to impedance discontinuities.

Application Note 2006-01-18

Limitations and Accuracies of Time and Frequency Domain Analysis of Physical Layer Devices

Application Note 2005-11-01

On-Chip Design Verification with Xilinx FPGAs
Xilinx Virtex-II Pro devices have redefined FPGAs.

Application Note 2003-04-30

Jitter Analysis Techniques for High Data Rates (AN 1432) - Application Note
This new application note describes the basic jitter measurements and the specific measurement techniques used in SONet/SDH/OTN and Gigabit Ethernet applications.

Application Note 2003-02-03

Understanding Signal Integrity
This is a technical note that was featured in the AMS Newsletter, Volume 1, Issue 2. This technical note discusses the problems that engineers have with signal integrity and solutions to help address the problems.

Application Note 2002-04-18

PDF PDF 287 KB
8 Hints for Debugging and Validating High-speed Buses
8 Hints for Debugging High-speed Buses

Application Note 2002-03-05

PDF PDF 2.24 MB
Designing and Validating High-Speed Memory Buses (AN 1382-2)
DDR SDRAM (double data rate synchronous dynamic random access memory) is quickly becoming an accepted technology in the PC (personal computer) industry. Its low cost, high performance, and increasingly wide availability make it very desirable for PC memory buses and embedded designs such as high...

Application Note 2001-12-20

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