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Keysight EEsof EDA Newsletter - Product and Application News
Keep tabs on the latest product and application news and review the archives of the Keysight EEsof EDA Newsletter.

Newsletter 2014-11-05

Modeling, Extraction and Verification of VCSEL Model for Optical IBIS AMI
A technique of modeling and extraction of VCSEL devices for IBIS-AMI has been proposed.

Article 2014-08-04

PDF PDF 1.18 MB
Improving IBIS-AMI Model Accuracy: Model-to-Model and Model-to-Lab Correlation Case Studies
This paper presents case studies for model-to-model & model-to-lab correlation methods & compares favorable/unfavorable factors for both methods. 10G, 11.5G and 23G SerDes data are used as examples.

Article 2014-02-18

PDF PDF 3.28 MB
Tips and Advanced Techniques for Characterizing a 28 Gb/s Transceiver
This paper shows the right combination of measurement and simulation techniques, and how the previously existing barriers for using de-embedding have been eliminated.

Article 2014-02-18

PDF PDF 3.82 MB
IBIS AMI Modeling of Retimer and Performance Analysis of Retimer based Active Serial Links
This paper presents a novel retimer modeling approach based on IBIS-AMI to capture the performance of a retimer that operates up to 15 Gbps.

Article 2014-02-18

PDF PDF 1.78 MB
De-Mystifying the 28 Gb/s PCB Channel: Design to Measurement
This paper demonstrates a design methodology for 28 Gb/s SERDES channels using Xilinx Virtex-7 Tx to show the required trade-offs that enable robust performance that is easy to verify with measurement.

Article 2014-02-18

PDF PDF 2.99 MB
Touchstone v2.0 SI/PI S-Parameter Models for Simultaneous Switching Noise (SSN) Analysis of DDR4
This paper presents a methodology to setup and analyze Simultaneous Switching Noise for DDR4 applications using Touchstone v2.0 models.

Article 2014-02-18

PDF PDF 8.07 MB
Mechanism of Jitter Amplification in Clock Channels
In this paper. jitter amplification in clock channels is analyzed analytically using the techniques developed in "Frequency domain analysis of jitter amplification in clock channels."

Article 2014-02-18

PDF PDF 671 KB
Follow Agilent EEsof EDA on Twitter!
Twitter enables you to keep current on news and updates with Agilent EEsof through the exchange of quick, frequent answers to one simple question: What are you doing?

Newsletter 2010-03-04

S-parameters Without Tears
This article explains s-parameter theory and shows how to create accurate, delay-causal, and passive time-domain models by combining band-limited s-parameter data with knowledge about the physical characteristics of a component.

Journal 2010-01-25

Practical Analysis of Backplane Vias - White Paper
This paper describes the methodology of using measurements on a test vehicle to build a high bandwidth, scalable model of long vias which includes the through and stub effects which can be used for system simulation.

Case Study 2009-04-20

PDF PDF 847 KB
Signal Integrity Simulation of PCI Express Gen 2 Channel
Article reprint from XrossTalk Magazine, Janurary 2009, author Jason Boh.

Article 2009-03-23

PDF PDF 1.81 MB
Inphi Delivers Memory Interface Chip for DDR3-1600 Using Advanced Design System
This Success Story details how Inphi delivered memory interface chip for DDR3-1600 using Keysight’s Advance Design System (ADS).

Case Study 2009-03-12

PDF PDF 196 KB
Signal Integrity Analysis and Simulation Tools include IBIS Models
This Article describes the types of models that need to be taken together for high-speed signal integrity analysis, and illustrates their use in a simulation of a high-speed memory circuit.

Article 2004-09-01

PDF PDF 411 KB