Analyze and Optimize 32- to 56- Gbps Serial Link Channels Webcast
1 Hour | Webcast - recorded | Where & When
WHAT IS THE WEBCAST ABOUT
SerDes design engineers often find themselves confronted with channels that prove quite difficult to optimize. “It is all about the margins”.
This webcast introduces a forensic channel analysis approach that implements both measurement hardware and EDA tools with contemporary SERDES internal tools (e.g., internal eye scan) for the purpose of optimizing the BER for highly pathological channels (i.e. identifying the major contributors to signal degradation in the link). State-of-the-art pulse response analysis such as this, provides valuable insight into the behavior of the channel and the effective use of CTLE, FFE, and DFE equalization techniques, in order to mitigate crosstalk, attenuation and return loss. Specific topics to be covered during this webcast include: optimization, BER, PAM-4, IBIS-AMI, S-parameters, causality, passivity, EQ, DFE, FFE, CTLE, and the latest in pulse response analysis and optimization.
WHO SHOULD ATTEND
Engineers and managers working on signal integrity design, characterization, and validation who want insight into the latest tips and techniques for optimizing the physical layer (package, PCBs & interconnects) for 32- to 56- Gbps communication links.
Al Neves, Chief Technologist, Wild River Technology
Alfred Neves is chief technologist at Wild River Technology. He has 31 years of experience in the design and application development of semiconductor products and capital equipment design focused on jitter and signal integrity analysis. Mr. Neves is and has been involved with the signal integrity community as a consultant, high-speed system-level design manager and engineer. Recent technical accomplishments include development of platforms to improve 3D electromagnetic correspondence to measure-based methods. He earned a bachelor’s degree in applied mathematics at the University of Massachusetts.
Jack Carrel, Applications Engineer, Xilinx.
Jack has over 25 years of experience in product development and design in the fields of Instrumentation, Test and Measurement, and Telecommunications. His background includes development of electro-optic modules, Multi-gigabit transceiver boards, high speed and high resolution data acquisition systems for government and commercial applications. Most recently he has been involved in product design using multi-gigabit transceivers with specific focus on PCB design issues. He has published in several professional publications. Jack received his Bachelor of Science degree in Electrical Engineering from the University of Oklahoma. Jack has been with Xilinx since 2006.
Heidi Barnes, Senior Application Engineer, Keysight Technologies
Heidi Barnes is a Senior Application Engineer for High Speed Digital applications in the EEsof EDA Group of Keysight Technologies, a spin-off of Agilent Technologies. Past experience includes over 6 years in signal integrity for ATE test fixtures for Verigy, an Advantest Group, and 6 years in RF/Microwave microcircuit packaging for KeysightTechnologies. She rejoined KeysightTechnologies in 2012, and holds a Bachelor of Science degree in electrical engineering from the California Institute of Technology.
Where & When
|Price||Location||For more information|
|Free||At Your PC||Enroll to view the January 26, 2017 recorded broadcast|
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