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High Speed Digital Seminar Tour 2017

WHY THIS SEMINAR IS IMPORTANT

In digital standards, every generational change introduces new challenges and risks. In this seminar, we will share our industry expertise and discuss solutions for high-speed digital design and test to help you anticipate these challenges, reduce risks and accelerate your designs. By attending this seminar, you will learn new design and test strategies for Signal Integrity/Power Integrity, USB/Type-C, 400G/PAM4, PCIe Gen4, DDR4/LPDDR4 as well as new data analytics tools.

WHAT TO EXPECT

There will be presentations focused on high-speed digital design and test and demonstrations by Keysight experts.

WHO SHOULD ATTEND

Design engineers, signal integrity engineers, quality engineers, validation engineers, test engineers, architects, project managers, program managers, application managers, and application engineers.

COST

Free

CO-SPONSORS

           

WHEN/WHERE

Tuesday, June 20

Radisson Hotel and Suites
Salon AB
10 Independence Drive
Chelmsford, MA 01824

Tuesday, June 27

DoubleTree Sunrise
13400 West Sunrise Boulevard
Sunrise, FL 33323

 

Thursday, June 29

Springhill Suites by Marriott
1128 Ledsome Lane
Cary NC 27511

AGENDA

8:30am - 8:55am     
Registration / Refreshments

8:55am – 9:05am
Introduction

9:05am – 10:20am
Signal Integrity and Power Integrity Engineering Design Techniques
The USB Type-C Gen1 (5 Gbps) and Gen2 (10 Gbps) channels are some of the more challenging architectures for digital design engineers due to the extreme rise-time of transitions between zeros and ones. The small physical size of this high density reversible connector increases the risk that design engineers will encounter unforeseen interoperability issues due to the physical layer. These problems can be avoided by leveraging measurements and simulations to adequately debug and characterize the performance driving interconnect features and fabrication tolerances. There are also unexpected power integrity challenges with the new 100 Watts of power delivery that must be dealt with in a logical manner. This seminar will show a step-by-step process that can be implemented by signal integrity engineers to assure their success designing with a high speed serial bus.

10:20am – 10:40am
Break

10:40am – 11:45am
PCI Express: Techniques for 16-Gbit Deployment
With PCI Express devices supporting speeds of up to 16 GBits per second, many new challenges arise in the area of signal integrity, transmitter signal quality, channel characterization and especially receiver sensitivity testing. In this session, we'll bring you up to speed on the tools and techniques you can use to be successful with your PCI Express 4.0 devices and specifically what you'll need to prepare for to test the physical layer, Gen4 requirements for your transmitter and receiver.

11:45am – 12:30pm
Lunch

12:30pm – 1:40pm
Making the Grade When Testing New 100G/400G Technology

With the adoption of new standards for high speed data transport in both electrical and optical links, the challenges are even greater in testing these transport links to meet the critical reliability necessary for Data Center applications. We will review several of the key factors that are being considered when testing this next generation technology and the instruments/tools changes that have been developed for debugging and proving the performance and efficiency of these technologies.

1:40pm – 2:00pm
Break

2:00pm – 3:00pm
Tools and Techniques for USB 3.1 Testing and Type-C Challenges
USB interfaces are commonly used in today's PCs, tablets, mobile phones and external storage devices. The USB 3.1 specification introduces many new opportunities and challenges for design and validation engineers. This presentation will provide practical tools and techniques for USB 3.1 transmitter and receiver testing that will assist ASIC and chipset designers to quickly deliver the next generation of USB-enabled devices. We will also cover the Type-C connector and address the challenge of validating designs employing this rapidly proliferating connector.

3:00pm - 4:00pm
Power and Signal Integrity Insight for DDR4/LPDDR4 Systems

Signal integrity and power integrity issues are often the root cause when systems don't behave as expected. Learn new techniques to gain rapid insight into power integrity and signal integrity in systems with high speed DDR4/LPDDR4 memory. Observe how to easily acquire cross-correlated measurements of traffic on DDR/LPDDR buses and the power integrity of systems. Innovative new probing of power usage and supply voltage fluctuations are used to correlate power usage and power integrity to specific areas of memory activity. End with a short discussion of making electrical compliance measurements consistent with JEDEC specifications.

4:00pm - 4:30pm
Test with Data Analytics to Enable Faster Time to Market

R&D designers perform many measurements to conclude if their designs meet limits whether set internally or by Standards committees. This short presentation will discuss how Keysight's new Data Analytics software capability addresses the needs of designers and their managers to be able to analyze their test results more quickly and in an intuitive manner. Attendees will learn how Keysight's Data Analytics software will enable them to make faster decisions and reduce time to market of their products.

4:30pm
Wrap-up