Order the DVD of the 2015 Education Forum (use your back key to return here)
Download Keysight's Papers Presented at the Technical Conference (use your back key to return here)
Keysight Technologies (formally Agilent’s Electronic Measurement Group) is proud to continue as the Host Sponsor for DesignCon. Keysight’s exhibit booth will be its first at DesignCon since spinning off from Agilent in November 2014. In addition to our host sponsorship, Keysight will be heavily engaged in DesignCon 2015 with our hands-on exhibit booth (#725), the Keysight Education Forum (KEF), and participation in 10 DesignCon technical papers.
This year, Keysight will highlight three key areas: DDR Memory, 100G ethernet and PAM4 technologies, and simulation and validation software.
• DDR Memory solutions will be highlighted through our hardware and software solutions in the booth and across the event, with industry experts delivering papers covering design, simulation and measurement challenges and solutions associated with DDR4 and LPDDR4. • KEF and technical sessions will highlight how to solve some of the toughest challenges associated with PAM-4 and 100G Ethernet, including IBIS-AMI modeling and simulation and how to successfully making 100G electrical measurements. Scroll down for KEF agenda.
• A broad range of simulation, modeling and compliance software solutions solving challenges across various digital technologies will be highlighted throughout the Keysight booth and KEF.
These technologies and more will be available in the Keysight Technologies’ booth #725. Keysight’s authorized technology partner, Electro Rent, will also be joining us in the DesignCon exhibit booth. Please stop by to talk to our leading industry experts and see hardware and software solutions, which focus on high speed digital solutions including: high performance oscilloscopes, logic analyzers, JBERTs, arbitrary waveform generators, power rail probes, TDR solutions, and countless valuable software applications. KEF is also available for all DesignCon attendees at no additional cost, so be sure to sign up on the DesignCon
|DesignCon 2015 Welcome Reception at Levi's Stadium - Sponsored by Keysight Technologies|
Tuesday, January 27, 2015: 6:30 PM – 9:00 PM
Dive into the DesignCon festivities! The Welcome Reception gives you the opportunity to network and re-connect with new members of the community and DesignCon alumni. Enjoy beer, wine, appetizers and much more! The welcome reception is open to paid attendees, speakers, media partners, TPC and exhibitors. Badges will be required for entry.
|DAY 1: Wednesday, January 28, 2015|
|8:30-9:10||USB 3.1 Gen 2 (10 Gbps) Physical Layer Test Challenges||
|Driven by the demand for more bandwidth, high speed digital standards continues to evolve to higher data rates. The USB 3.1 specification delivers more than double the practical data rate compared to the current 5 Gbps USB 3.0, by implementing a more efficient data encoding scheme. This results in even tougher requirements for the physical layer to ensure interoperability at 10 Gbps. In this session, we will provide an overview of the physical layer design and test challenges for the USB 3.1 transmitter, receiver, and cable.|
|9:20-10:00||Practical Guide to Quickly Making 100G Electrical Measurements||
|Characterizing and validating compliance of 100G Ethernet digital links can be daunting and time consuming, driven by a wide range of test parameters and conditions. After carefully setting up the device, clock recovery, error detection, and test parameters, the user is still faced with understanding standards documents like IEEE 802.3-2012/bj/bm, and interpreting the results. This session will highlight the wide range of Keysight solutions to test electrical parameters, showing you how to quickly set up the measurements, obtain repeatable results and gain insights to improve device performance and yields.|
|10:15-10:55||PCIe protocol analysis for SSDs||Don Schoenecker||Implementing SSDs on the PCIe interface offers large performance gains. To maximize throughput, you need to carefully tune the operation of the PCIe protocols. This presentation will discuss the operation of power saving, link state management and Flow Control credits that will impact design decisions. PCI express Solid State Drives (PCIe SSDs) provide significant performance benefits in enterprise storage applications compared to traditional hard disc drives (HDDs) and SSDs. The emergence of non-volatile memory express (NVMe), a scalable host controller protocol developed for PCIe SSDs, provides an efficient and streamlined command set, which even further enhances storage throughput. Learn about implementation and validation methods including an overview of protocols, operation of PCIe link states and transaction levels, and how tuning the operation of the PCIe protocols improves the storage performance.|
|11:05-11:45||Power Integrity Solution - Choosing the Right Measurement and Simulation Tools||
The DC power supply is receiving more and more scrutiny and the supply tolerances are getting tighter as users try to decrease power, increase yield and minimize supply induced signal noise. We will discuss tools and techniques for making power integrity measurements such as ripple, noise, spikes, compression, static/dynamic load response and supply induced signal noise and signal jitter. Included is a discussion of the effects of oscilloscope noise, probe noise, probe attenuation ratio, offset range, input range, connection technique and measuring supply/signal crosstalk.
We will also review high-capacity EM simulation to analyze the impact of “non-ideal ground” and power plane noise. Key enablers include the ability to process a large PCB layout to select critical nets easily, to complete the EM model extraction quickly, and to assist in problem diagnosis and fix through, for example, decoupling capacitor optimization. Static and dynamic IR drop analyses can help the designer visualize voltage and current distributions through planes and vias, detect power plane resonances, extract resistance value, and then based on that information to improve system design.
|12:00-12:45||DDR4/LPDDR4: Overcome the Barriers of Simulating, Testing and Probing High-Speed Memory Systems||
|The DDR4 and LPDDR4 specification have yet another increase in data rates up to 3733 MT/s. Memory system designers need a more reliable way to gain access to the key signals of their system to perform compliance testing and characterization. Additionally, for the first time in a DDR standard, JEDEC has included in a BER contour spec for DDR4. This specification presents new simulation and measurement challenges. We will discuss ways to overcome simulation, probing and test challenges when working with DDR4 and LPDDR4 memory systems.|
|DAY 2: Thursday, January 29, 2015|
|8:30-9:10||Tips and Techniques to Characterize Signal Integrity Problems Quickly and Accurately||
|On today’s high-speed digital designs, signal integrity issues such as reflections, excessive losses, and crosstalk can degrade system performance. This session will show you how use TDR/TDT in both simulations and measurements. Special tips and techniques will be demonstrated, such as the power of simple TDR/TDT simulations, using 1-port Automatic Fixture Removal (AFR), and Electronic Calibration (ECal) for TDR/TDT, that help engineers characterize and troubleshoot SI issues with greater measurement accuracy.|
|9:20-10:00||Simulation and Characterization of PAM-4 signals in 28G and 56G Designs||
|400 Gb/s links will be the next step in the continuing need for increased network bandwidth in data centers. Multi-level signaling formats such as PAM-4 are an enabling technology to implement 400G. The switch from NRZ to PAM-4 is revolutionary, rather than evolutionary from 100G, presenting many new concepts and design challenges. This session will discuss PAM-4 solutions that address simulation and measurement needs for 28G and 56G Designs.|
|10:15-10:55||Gain Insight into DDR3/4 and LPDDR3/4||Jennie Grosslight||
As designers engage with the latest DDR4 and LPDDR4 memory technologies that increase system data rates beyond 2400Mb/s, new challenges arise as designs are being pushed to record speeds. See the latest test and measurement techniques to address these challenges and minimize design risk. Gain complete insight into the actual behavior of the memory system by using a logic analyzer to follow signal flow of DDR3/4 and LPDDR3/4 signals. Learn to overcome challenges in debugging, validating and proving interoperability.
Access to DDR4 and LPDDR4 memory signals for signal integrity characterization is beyond challenging. Explore a paradigm shift in DDR memory test techniques; learn about time saving bus level signal integrity insight and see case study examples showing how to use this insight to speed up your debug efforts on DDR memory systems.
Bus level signal integrity insight provides qualitative eye scans for up to hundreds of signals in a DDR memory system all relative to each other, captured under the same probing conditions. This presentation will cover the basic theory and techniques used to provide qualitative Bus Level Signal Integrity Insight from eye scans created on a logic analyzer. The differences between qualitative and quantitative results will be explained and examples provided.
|11:05-11:45||Surmounting the Challenges of 16 Gigabit Operation with PCI Express||
|The move to data transfer speeds of 8 gigabits per second and beyond ushered in a new era for PCI Express designers who had to overcome the physical test challenges of receiver equalization and complicated feedback mechanisms for controlling transmitter equalization. In addition shorter unit intervals and channel insertion loss reduce operating margins considerably. We’ll bring you up to speed on the ways you can be successful with PCI Express designs operating at speeds up to 16 gigabit per second and what you’ll need to prepare for in physical layer validation for transmitter and receiver testing. In addition, we will describe a new approach to compliance that uses the same software tools you use for device characterization but using data provided by simulation instead of physical measurement. The simulation mimics a real hardware test bench, and it emits the same waveforms that the oscilloscope app expects when testing in the lab. This allows you to verify the pre-manufacture simulated design with the actual post-manufacture prototype.|
|12:00-12:40||Addressing the challenges of PAM-4 receiver stressed input testing||Steve Sekel||The switch to PAM-4 signaling is revolutionary in many aspects, including receiver input testing. The traditional jitter and amplitude stress types which have been used for years in NRZ do not emulate the impairments which cause problems in PAM-4. This session will cover new pattern generation solutions which offer the flexibility to create the new stress types needed for “deep” characterization of PAM-4 devices, including those devised by the users themselves.|
Design Con's site: www.designcon.com/santaclara