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17_EV_076384 Understanding Insights and Overcoming High Speed Design Challenges

0.5   Day | Seminar | Where & When

About the Seminar

Every generation change in digital interconnect standard (e.g. DDR, PCIe, USB Type C, SATA etc.) introduces faster connectivity between electronics devices. It also brings along new design challenges, in particular, issues with Signal Integrity (SI) and Power Integrity (PI) on the PCB designs. Design success demands that today’s engineer have the skills needed to overcome these challenges and face down any risks. In this seminar, Keysight experts will share their industry expertise and present design, analysis and simulation solutions for effectively addressing signal integrity and power integrity challenges.

Who should Attend

  • PCB designers wanting to gain a greater knowledge of VIAs and how to properly utilize them in PCB design
  • PCB designers wanting to gain a greater knowledge of thermal issues in PCBs
  • Power Integrity engineers
  • Engineers who need to analyze and simulate crosstalk in their high-speed digital designs

Speakers

Mr. Hee-Soo Lee, 3D EM Applications Specialist.

Hee-Soo Lee holds a BSEE degree from the Hankuk Aviation University, Korea. He has more than 20 years of design and simulation experience in the area of RF and Microwave designs, and is currently the Applications Specialist for 3D EM solutions at Keysight EEsof EDA.

Mr. Brian Yeo, High Speed Digital Application Consultant of Keysight Technologies

Brian Yeo is the Application Consultant of Keysight. He first joined Agilent Technologies as Online Technical Support engineer covering Greater China region. He is now responsible for the digital application support for South Asia Pacific region. Prior to Agilent/Keysight, he was the R&D engineer with Avago Technologies in the Optical Sensors division. Brian graduated from Nanyang Technological University with a B.Eng in EEE.

Agenda

Time Description
0830-0900 Registration
0900-0910 Welcome Speech from Keysight Technologies
0910-1010 Demystifying VIAs in High-Speed PCB Design
1010-1030 Coffee/Tea Break
1030-1130 Thermal Effects, Power Integrity and Your PCB
1130-1230 Addressing Crosstalk Challenges from Design Simulation to Actual Board Analysis and Debug
1230-1330 Lunch

Paper Abstracts

Demystifying VIAs in High-Speed PCB Design

A high-speed signal traveling vertically through the board layer is several times more complex and difficult to analyze than a signal traveling horizontally along the same layer. This presentation covers the basics of VIA construction and its impact to high-speed signals. We will also highlight tips for better VIA design and introduce different simulation techniques for generating more transparent interconnects and allow you to make various tradeoffs.

Thermal Effects, Power Integrity and Your PCB

Did you know that in addition to validating the electrical performance of the power integrity on your PCB, it is also crucial to perform a thermal validation as well? In this topic we will introduce the thermal aspects of power integrity in your PCB designs and why it is critical to consider them. To better understand a design’s power integrity from the thermal viewpoint, it provides a theoretical background for heat transfer and an overview of the thermal analysis technologies. Finally, we will demonstrate the importance of performing thermal analysis on PCB designs by showing a practical PCB design example.

Addressing Crosstalk Challenges from Design Simulation to Actual Board Analysis and Debug

Crosstalk is becoming a huge challenge in today’s design due to higher signal transfer rate in very compact designs. Crosstalk can corrupt the data transmission, closes the signal eye opening, adds jitter to the signal and increases bit errors which will affect the operation of your product. There can be many type of crosstalk aggressors, which includes adjacent transmission lines, power supplies, phase lock loops and reference clocks. Identifying and minimizing crosstalk early through simulation and analysis is critical to reduce the board spins at the product level. If crosstalk is present in the board you are measuring and affecting your design, effective tools are needed to quickly and effectively analyze and debug the issues. This presentation will provide the tools and insights how to solve crosstalk challenges from simulation to actual board analysis and debug.
 

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Registration

Please register online before 20 Oct 2017

This seminar is free of charge.  Seats are limited and registration is subject to availability and confirmation. Keysight Technologies reserves the right to reject any registration request, reschedule or cancel the event.

We will revert on the status of your registration within a week. Thank you for your patience.

Where & When

Price Date(s) Location Phone Fax For more information
Free 2017-11-03 08:30 — 2017-11-03 13:30
Local Time
Nanyang Polytechnic  1800 375 8100 6755 0042 Enroll Online

Prices shown are list prices and are subject to change without notice.