High-speed ADC chipsets benefit from optimized components
Keysight digitizers are based on proprietary application-specific integrated circuits (ASICs) that optimize the performance of data-conversion systems that include high-speed ADC (analog-to-digital converter) and flash ADC devices. These chipsets are integrated into our range of modular high-speed digitizers and are ideal for the high-precision, high-speed, power-sensitive applications in which they are utilized. The ASICs were designed specifically to optimize and enhance the performance of high-speed and flash ADC chips in the gigahertz frequency range.
Leveraging purpose-built components
The front-end ADC chipset integrates signal conditioning, amplification, triggering and interleaving—functions essential to high-speed data acquisition—into a pair of companion ASIC devices. The front-end amplifier (FEA) chip provides signal conditioning and amplification to the optimum voltage levels for the subsequent high-speed and flash ADC components. This FEA circuit also includes a bandwidth-limiting filter, which reduces signal noise.
Input signals acquired on multiple channels and through multiple FEAs are routed to a cross-point switch chip that allows interleaving of up to four high-speed ADC devices. After conversion by a high-speed ADC, the digitized signal can then be stored in acquisition memory or undergo processing with a field-programmable gate array (FPGA).
A clock and memory ADC chip provides the vital clock and synchronization signals; it also captures and memorizes data acquired with the high-speed or flash ADC and does so with maximum throughput. The clock ASIC includes the functions needed to build the timebase system of a multi-ADC acquisition system. With a clock generator and a clock distribution circuit, up to four high-speed ADCs can be interleaved to sample at up to 10 GSa/s.
The synchronization of multiple clock circuits is made possible with special clock inputs and outputs. The acquisition and memory controller ASIC is designed for the capture and memorization of up to the 20-bit digital data typically generated by high-speed ADC devices at speeds of up to 2 Gbyte/s. The design uses large internal static RAM and high clock frequencies, and is able to accept and generate low-voltage differential signal (LVDS) levels for the fast input/output signals.
Enhancing overall test performance
The technology embedded in our high-speed and flash ADC chips and digitizer modules provides exceptional performance: shorter measurement time, faster testing and lower cost per measurement. Smaller size and lower power consumption help enable systems with a small footprint and greater uptime (lower MTBF).
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