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高速デジタル

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デジタル規格では、世代交代のたびに新たなリスクが生じます。弊社の製品を開発したり、皆様のようなエンジニアの方々と一緒に仕事をしているときに、リスクに直面してきました。Keysightの高速デジタル・テスト用ソリューション・セットは、業界の専門家との継続的な関係に基づいて、測定機器とボードの専門知識を組み合わせたものです。弊社は最新の経験を提供することにより、問題を予測でき、優れた製品を短期間で作成できるように支援しています。Keysightが、最高のデザインの実現を支援。

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ADS Videos on YouTube 
Advanced Design System (ADS) Video Library playlist in Keysight EEsof EDA's Channel on YouTube

デモ 2014-08-06

 
High Speed Digital Design and Simulation Videos on YouTube 
Keysight EEsof EDA's High Speed Digital Design and Simulation video playlist on YouTube.

デモ 2014-08-06

 
Modeling, Extraction and Verification of VCSEL Model for Optical IBIS AMI 
A technique of modeling and extraction of VCSEL devices for IBIS-AMI has been proposed.

記事 2014-08-04

PDF PDF 1.18 MB
EDA Support Services 
Keysight Support Services for EDA Products offers customers several benefits otherwise not available. This service is designed to help you get the most out of your software purchases.

ブローシャ 2014-08-03

PDF PDF 465 KB
Keysight EEsof EDA Software and Modular Solutions for Universities 
Keysight works in collaboration with universities to provide tools that enable education and research for the engineers of tomorrow. The brochure outlines available programs, software and hardware.

ブローシャ 2014-08-03

PDF PDF 1.44 MB
Analysis of Test Coupon Structures for the Extraction of High Frequency PCB Material Properties 
Exploration of the addition of Beatty series resonant impedance structures to improve the accuracy of extracting PCB material properties for the purpose of constructing 3D-EM simulations.

アプリケーション・ノート 2014-08-03

PDF PDF 2.19 MB
RF and Microwave Industry-Ready Student Certification Program 
This program confirms a student’s technical knowledge, design expertise, and hands-on measurement proficiency in the use of Keysight EEsof EDA software design tools and Keysight instruments.

ブローシャ 2014-08-03

PDF PDF 576 KB
Controlled Impedance Line Designer in ADS 
The Controlled Impedance Line Designer in ADS enables signal integrity engineers to do pre-layout controlled impedance line design by optimizing the substrate stack up and the transmission line geometry.

デモ 2014-08-01

 
New ADS DDR4 Compliance Test Bench for Solving the Simulation-Measurement Correlation Challenge 
Agilent introduces Advanced Design System DDR4 Compliance Test Bench, which enables a complete workflow for DDR4 engineers from simulation of a candidate design through measurement of the finished prototype. The solution is ideal for semiconductor companies developing DDR controller IP; those developing DRAM chips and DIMMs; and OEMs integrating the controller and DIMM into a system using PCB technology.

プレス資料 2014-06-30

 
DDRメモリのデザイン/テストの概要 
DDRデザインは、インターコネクト・デザイン、アクティブ信号検証、プロトコル検証、ファンクション・テストの4つに分割できます

ブローシャ 2014-06-03

PDF PDF 571 KB
Network Analyzer Time Domain Reflectometry (TDR) Measurements – Granite River Labs 
Network Analyzer Time Domain Reflectometry (TDR) Measurements from Granite River Labs and Keysight

ソリューション概要 2014-04-29

 
Discovering ADS 
A collection of Keysight EEsof EDA ADS video demonstrations and tutorials

デモ 2014-03-20

 
Digital Design & Interconnect Standards - Brochure 
Brochure shows Keysight’s high-speed digital solution set , a range of essential tools, measurement and simulation—that will help cut through the challenges of gigabit digital designs.

ブローシャ 2014-02-20

PDF PDF 6.47 MB
ADS 2014 Dramatically Improves Design Productivity and Efficiency 
Agilent announces a powerful new version of Advanced Design System software, ADS 2014. Designed to dramatically improve design productivity and efficiency with new technologies and capabilities, ADS 2014 is the software's most significant ADS release to date.

プレス資料 2014-02-20

 
Mechanism of Jitter Amplification in Clock Channels 
In this paper. jitter amplification in clock channels is analyzed analytically using the techniques developed in "Frequency domain analysis of jitter amplification in clock channels."

記事 2014-02-18

PDF PDF 671 KB
Touchstone v2.0 SI/PI S-Parameter Models for Simultaneous Switching Noise (SSN) Analysis of DDR4 
This paper presents a methodology to setup and analyze Simultaneous Switching Noise for DDR4 applications using Touchstone v2.0 models.

記事 2014-02-18

PDF PDF 8.07 MB
IBIS AMI Modeling of Retimer and Performance Analysis of Retimer based Active Serial Links 
This paper presents a novel retimer modeling approach based on IBIS-AMI to capture the performance of a retimer that operates up to 15 Gbps.

記事 2014-02-18

PDF PDF 1.78 MB
De-Mystifying the 28 Gb/s PCB Channel: Design to Measurement 
This paper demonstrates a design methodology for 28 Gb/s SERDES channels using Xilinx Virtex-7 Tx to show the required trade-offs that enable robust performance that is easy to verify with measurement.

記事 2014-02-18

PDF PDF 2.99 MB
Improving IBIS-AMI Model Accuracy: Model-to-Model and Model-to-Lab Correlation Case Studies 
This paper presents case studies for model-to-model & model-to-lab correlation methods & compares favorable/unfavorable factors for both methods. 10G, 11.5G and 23G SerDes data are used as examples.

記事 2014-02-18

PDF PDF 3.28 MB
Tips and Advanced Techniques for Characterizing a 28 Gb/s Transceiver 
This paper shows the right combination of measurement and simulation techniques, and how the previously existing barriers for using de-embedding have been eliminated.

記事 2014-02-18

PDF PDF 3.82 MB
Sanjay Gangal of EDACafé interviews Colin Warwick on New SI and EM Products at Designcon 2014 
Sanjay Gangal, V.P. Sales & Marketing at EDACafé interviews Colin Warwick, Product Manager at Keysight Technologies, at Designcon 2014, .

デモ 2014-02-04

 
ADS Controlled Impedance Line Designer Solves Key Challenges in Designing Chip-to-Chip Links 
Agilent introduces Agilent EEsof EDA’s Controlled Impedance Line Designer. The software product quickly and accurately optimizes stack up and line geometry for multigigabit-per-second chip-to-chip links, using the most relevant metric.

プレス資料 2014-01-27

 
Agilent Technologies to Exhibit Digital Design and Test Solutions at DesignCon 2014 
Agilent announced it will exhibit its high-speed digital solutions shown at DesignCon 2014, Jan. 29-30, Booth 201, in Santa Clara. The products offer a wide range of essential tools to help engineers design, simulate, analyze, debug and achieve compliant designs while meeting the challenges of gigabit digital designs.

プレス資料 2014-01-22

 
Quick Start for Signal Integrity Design Using Advanced Design System (ADS) 
This demo guide is a part of the high-speed digital design workflow for signal integrity engineers using Advanced Design System.

技術概要 2014-01-20

PDF PDF 3.80 MB
ジッタ分離を用いた高速デジタル・デザイン向けシミュレーションの革新的ワークフロー 
この記事では、ジッタ分離解析用の新しいシミュレーション・ワークフローを紹介します。

アプリケーション・ノート 2013-11-26

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