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Digital Design & Interconnect Standards

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In digital standards, every generational change puts new risks in your path. We see it first hand when creating our products and working with engineers like you. Keysight’s solution set for high-speed digital test is a combination of instrumentation and broad expertise built on our ongoing involvement with industry experts. By sharing our latest experiences, we can help anticipate challenges and accelerate your ability to create products you’ll be proud of.

Keysight - Insights for your best design

Achieve signal integrity in high-speed design with these useful tools, demos, videos and more . Learn more about Digital Design & Interconnect solutions from Keysight. 
 

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Signal Integrity: Include Post-layout PCB Artwork into your Eye Diagram and BER Contour Simulation 
Originally broadcast May 5, 2010. Part of the Series: Signal Integrity for High Speed Digital Interconnects.

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Extreme Oscilloscope Probing Webcast 
Original broadcast December 4, 2013

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Using IBIS AMI Models as ‘Executable Data sheets’ in High Speed Digital Interconnect Simulations 
Originally broadcast Sept 9, 2010. Part of the Series: Signal Integrity for High Speed Digital Interconnects.

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Keeping up with 10G USB 3.1 Physical Layer Test Challenges Webcast 
Original broadcast January 15, 2014

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Using Logic Analysis to Find Root Cause of Digital Design Errors Webcast 
Recorded broadcast December 17, 2013

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Accelerate DDR4/LPDDR3 Memory Debug with Bus level Signal Integrity Insight Webcast 
Original broadcast March 4, 2014

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Innovations in EM Simulation for High Speed Digital Design 
Original broadcast Nov 18, 2010; Part of the Series: Signal Integrity for High Speed Digital Interconnects.

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PCI Express 3.0 Compliance - Successfully Navigating the Standard Webcast 
Original broadcast May 7, 2013

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PCI Express 3.0 Receiver test of ASICs- how to face this challenge - webcast 
When PCIe 3.0 was generated, it was a goal to re-use the existing passive infrastructure - the channels. With nearly double the signal rate (8Gb/s vs. 5Gb/s), the error free transmission now heavily depends on the RX. Therefore it is now normati...

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Physical Layer design challenges for PCI Express® 3.0 and 2.0 designs 
You will learn advanced techniques for PCI Express phy-layer validation covering the latest PCIe 3.0 specification requirements as well as practical extensions to PCIe 2.0 and 1.1 designs. This seminar analyzes transmitter and receiver performance.

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MIPI Physical Layer Transmitter Test Solutions Webcast 
Original broadcast April 2, 2014

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EMC Back to Basics Webcast 
Original broadcast April 16, 2014

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Addressing Design and Test Challenges for the New LTE-Advanced Standard Webcast 
Original broadcast July 15, 2014

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Case Study: Overcoming Return-path Discontinuity in DDR3/GDDR5 Memory Controller Packages 
Original broadcast October 13, 2011

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Vector Modulation and Frequency Conversion Fundamentals Webcast 
Original broadcast July 18, 2013

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Fixturing and Fixture Removal for Multiport Devices with Non-Standard RF Interfaces Webcast 
Original broadcast March 11, 2014

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Simultaneous Switching Noise Analysis in DDR4 applications using Power-Aware IBIS Models Webcast 
Original broadcast May 22, 2014

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ADS in 3D: Speed Your Design with Integrated 3D EM Simulation 
Originally broadcast March 24, 2010

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Basics of RF Amplifier Test With the Vector Network Analyzer 
Original broadcast Mar 13, 2012

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Innovations in EDA: Multi-Technology RF Design Using the New Advances in ADS 2011 
Originally broadcast March 1, 2011

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New Calibration Method Simplifies Measurements of Fixtured Devices Webcast 
Original broadcast July 29, 2014

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Breakthrough Developments in TDR/TDT Measurement Technology Webcast 
Original broadcast May 7, 2014

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Fixture De-embedding Techniques for 28 Gb/s Transmitter Measurements Webcast 
Live broadcast January 23, 2014; 10am PT/1pm ET/19:00 CET

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Network Analysis Back to Basics Webcast 
Recorded broadcast August 21, 2013

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SFP+ and 10GBASE-KR Transmitter Compliance Testing using an Oscilloscope Webcast 
Original broadcast February 19, 2014

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