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Digital Design & Interconnect Standards

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In digital standards, every generational change puts new risks in your path. We see it first hand when creating our products and working with engineers like you. Keysight’s solution set for high-speed digital test is a combination of instrumentation and broad expertise built on our ongoing involvement with industry experts. By sharing our latest experiences, we can help anticipate challenges and accelerate your ability to create products you’ll be proud of.

Keysight - Insights for your best design

Achieve signal integrity in high-speed design with these useful tools, demos, videos and more . Learn more about Digital Design & Interconnect solutions from Keysight. 
 

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Accelerate DDR4/LPDDR3 Memory Debug with Bus level Signal Integrity Insight Webcast 
Original broadcast March 4, 2014

Webcast - recorded

 
Accelerate FPGA Debug by Applying Latest Tools and Methods Webcast 
Original broadcast June 10, 2014

Webcast - recorded

 
Best practices in implementing boundary scan on limited access boards 
Live broadcast December 18, 2014; 9am PT / 12pm ET

Webcast

 
Boundary Scan Webcast Series 
Live and on-demand webcasts

Webcast

 
Common DFT guidelines for implementing boundary scan on limited access boards webcast 
Original broadcast September 11, 2014

Webcast - recorded

 
DesignCon 2014 
Jan 28-31, 2014; Santa Clara Convention Center Download papers presented, order the AEF DVD

Tradeshow

 
Embedded testing of Intel Haswell and Broadwell chipsets on limited access client boards webcast 
Live broadcast November 13, 2014; 9am PT / 12pm ET

Webcast

 
EMI/EMC Analysis for High-Speed Digital Design Webcast 
Live broadcast July 24, 2014; 10am PT/1pm ET/19:00 CET

Webcast

 
Extending boundary scan tests to improve test coverage of limited access boards webcast 
Original broadcast September 25, 2014

Webcast - recorded

 
Fixture De-embedding Techniques for 28 Gb/s Transmitter Measurements Webcast 
Live broadcast January 23, 2014; 10am PT/1pm ET/19:00 CET

Webcast - recorded

 
Fixturing and Fixture Removal for Multiport Devices with Non-Standard RF Interfaces Webcast 
Original broadcast March 11, 2014

Webcast - recorded

 
How to Achieve Compliance to the New 1E-16 BER Contour Spec in DDR4 
Live broadcast November 6, 2014; 10am PT/1pm ET

Webcast

 
How to Optimize Your SerDes Design During the Pre-layout Phase Webcast 
Original broadcast September 25, 2014

Webcast - recorded

 
Introduction to the Keysight x1149 Boundary Scan Analyzer Webcast 
Original broadcast August 26, 2014; 9am PT / 12pm ET

Webcast - recorded

 
Maximizing test coverage of multiple limited access boards by linking multiple boundary scan chains 
Original broadcast October 9, 2014

Webcast - recorded

 
New Calibration Method Simplifies Measurements of Fixtured Devices Webcast 
Original broadcast July 29, 2014

Webcast - recorded

 
Next generation BERT Ensures Signal Integrity in High-speed Digital Designs Webcast 
Original broadcast January 21, 2014

Webcast - recorded

 
Simulation-Measurement Workflow for DDR Compliance Webcast 
Original broadcast March 27, 2014

Webcast - recorded

 
Simultaneous Switching Noise Analysis in DDR4 applications using Power-Aware IBIS Models Webcast 
Original broadcast May 22, 2014

Webcast - recorded

 
Testing DDR on limited access boards using boundary scan silicon nails 
Live broadcast October 30, 2014; 9am PT / 12pm ET

Webcast

 
Testing limited access SSD boards with boundary scan and external instruments webcast 
Live broadcast December 4, 2014; 9am PT / 12pm ET

Webcast

 
Tips to Debugging DDR 1, 2 and 3 Physical and Protocol Layer Issues webcast 

Training Materials 2009-01-06

 
Using Logic Analysis to Find Root Cause of Digital Design Errors Webcast 
Recorded broadcast December 17, 2013

Webcast - recorded