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Digital Design & Interconnect Standards

In digital standards, every generational change puts new risks in your path. We see it first hand when creating our products and working with engineers like you. Keysight’s solution set for high-speed digital test is a combination of instrumentation and broad expertise built on our ongoing involvement with industry experts. By sharing our latest experiences, we can help anticipate challenges and accelerate your ability to create products you’ll be proud of.

Keysight - Insights for your best design

Learn more about Digital Design & Interconnect solutions from Keysight. 
 

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Signal Integrity Tips and Techniques Using TDR, VNA and Modeling - Article Reprint  
Time and frequency domain analyses for simulation and measurements provide quick solutions for characterizing signal losses and identifying elements that control performance.

Article 2016-03-31

PDF PDF 644 KB
Solving Electronics Design Challenges of an Aerospace System with EDA Tools  
Microwave Product Digest featured article on solving electronics design challenges of an aerospace system using EDA tools.

Article 2016-03-22

 
Keysight EEsof EDA makes it easy to get back to school—at least virtually 
Rick Nelson, executive editor of Evaluation Engineering, visited Keysight Technologies and had this to say about Keysight EEsof EDA.

Article 2015-09-11

 
Challenges extend from simulation to compliance 
Tami Pippert, Keysight Technologies’ high-speed digital marketing program manager, elaborates on how Keysight is enhancing its model generation, simulation, and data analysis technologies.

Article 2015-07-08

 
Improving IBIS-AMI Model Accuracy: Model-to-Model and Model-to-Lab Correlation Case Studies - Articl 
This DesignCon 2014 paper presents case studies for model-to-model & model-to-lab correlation methods & compares favorable/unfavorable factors for both methods. 10G, 11.5G and 23G SerDes data are used as examples.

Article 2015-04-02

PDF PDF 3.34 MB
Mechanism of Jitter Amplification in Clock Channels 
In this paper. jitter amplification in clock channels is analyzed analytically using the techniques developed in "Frequency domain analysis of jitter amplification in clock channels."

Article 2014-08-04

PDF PDF 715 KB
IBIS AMI Modeling of Retimer and Performance Analysis of Retimer based Active Serial Links 
This paper presents a novel retimer modeling approach based on IBIS-AMI to capture the performance of a retimer that operates up to 15 Gbps.

Article 2014-08-04

PDF PDF 1.88 MB
De-Mystifying the 28 Gb/s PCB Channel: Design to Measurement 
This paper demonstrates a design methodology for 28 Gb/s SERDES channels using Xilinx Virtex-7 Tx to show the required trade-offs that enable robust performance that is easy to verify with measurement.

Article 2014-08-04

PDF PDF 2.84 MB
Touchstone v2.0 SI/PI S-Parameter Models for Simultaneous Switching Noise (SSN) Analysis of DDR4 
This article reprint presents a methodology to setup and analyze Simultaneous Switching Noise for DDR4 applications using Touchstone v2.0 models.

Article 2014-08-04

PDF PDF 8.20 MB
Modeling, Extraction and Verification of VCSEL Model for Optical IBIS AMI 
A technique of modeling and extraction of VCSEL devices for IBIS-AMI has been proposed.

Article 2014-08-04

PDF PDF 1.18 MB
Tips and Advanced Techniques for Characterizing a 28 Gb/s Transceiver 
This paper shows the right combination of measurement and simulation techniques, and how the previously existing barriers for using de-embedding have been eliminated.

Article 2014-02-18

PDF PDF 3.82 MB
Signal Integrity Simulation of PCI Express Gen 2 Channel 
Article reprint from XrossTalk Magazine, Janurary 2009, author Jason Boh.

Article 2009-03-23

PDF PDF 1.81 MB
Signal Integrity Analysis and Simulation Tools include IBIS Models 
This Article describes the types of models that need to be taken together for high-speed signal integrity analysis, and illustrates their use in a simulation of a high-speed memory circuit.

Article 2004-09-01

PDF PDF 411 KB