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Digital Design & Interconnect Standards

In digital standards, every generational change puts new risks in your path. We see it first hand when creating our products and working with engineers like you. Keysight’s solution set for high-speed digital test is a combination of instrumentation and broad expertise built on our ongoing involvement with industry experts. By sharing our latest experiences, we can help anticipate challenges and accelerate your ability to create products you’ll be proud of.

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Learn more about Digital Design & Interconnect solutions from Keysight. 

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Keysight EEsof EDA Newsletter - Product and Application News 
Keep tabs on the latest product and application news and review the archives of the Keysight EEsof EDA Newsletter.

Newsletter 2017-08-01

 
S-parameters: Signal Integrity Analysis in the Blink of an Eye 
This article discusses new concepts for serial link design and analysis as applied to physical layer test and measurement techniques. Novel test fixtures and signal integrity software tools will be discussed in real world applications in the form of design case studies.

Article 2017-05-30

 
The Melting Trace Paradox 
Unlike other famous paradoxes such as the Zeno’s paradox, where Achilles and the Tortoise are involved, the melting trace paradox is one with a segment of copper trace and a current source.

Article 2017-05-24

 
Ensuring High Signal Quality in PCIe Gen3 Channels 
This Signal Integrity Journal article written by Keysight engineer, Anil Kumar Pandey includes the challenges of maintaining transmission channel signal quality in today's PCIe Gen3 Channels.

Article 2017-03-14

 
Accurate Statistical-Based DDR4 Margin Estimation Using SSN Induced Jitter Model 
This paper proposes a methodology, that improves the accuracy of DDR4 statistical simulation, by using the mask correction factor.

Journal 2017-03-04

 
Heidi Barnes: DesignCon 2017 Engineer of the Year 
EDN Network's Martin Rowe interviews Heidi Barnes, DesignCon 2017 Engineer of the Year.

Article 2017-02-23

 
8 Steps to a Successful DDR4 Design 
Learn how Keysight's design flow example for DDR4 can help you achive confidence in your design and help you ensure success.

Journal 2016-10-20

 
A Quick Fix for Poor Capacitor, Inductor and DC/DC Impedance Measurements  
Modern Test & Measure article by Steve Sandler (Picotest) explains why you need an extended range, partial S2p measurement and how to make this improved measurement.

Article 2016-10-03

 
Best Practices for Connector Models 
Eric Bogatin, Signal Integrity Journal Editor, discusses best practices for connector modeling and measuring with Heidi Barnes, Keysight ADS application engineering specialist, and Jim Nadolny, Principle SI Engineer for Samtec.

Article 2016-09-30

 
Correlating simulation and measurement for a USB Type-C reference channel (Part 1) 
This article from Electronic Products discusses a step-by-step process that signal integrity engineers can follow to ensure their success in designing with USB Type-C devices.

Article 2016-09-21

 
Follow Keysight EEsof EDA on Twitter! 
Twitter enables you to keep current on news and updates with Keysight EEsof through the exchange of quick, frequent answers to one simple question: What are you doing?

Newsletter 2016-07-14

 
Signal Integrity Tips and Techniques Using TDR, VNA and Modeling - Article Reprint  
Time and frequency domain analyses for simulation and measurements provide quick solutions for characterizing signal losses and identifying elements that control performance.

Article 2016-03-31

PDF PDF 644 KB
The PDN Bandini Mountain and Other Things I Didn’t Know I Didn’t Know 
"In engineering, it's what you don't know you don't know that can ruin your day and keep you awake at nights." From Bert Simonovich's practical design notes.

Journal 2016-03-30

 
Solving Electronics Design Challenges of an Aerospace System with EDA Tools  
Microwave Product Digest featured article on solving electronics design challenges of an aerospace system using EDA tools.

Article 2016-03-22

 
Minimizing Design Risk, Shortening Development Time of a Digital Transmission System 
Powerful design and simulation software provides valuable insights to help uncover and solve difficult design challenges at every stage of the design process.

Case Study 2015-12-15

PDF PDF 1.17 MB
Keysight EEsof EDA makes it easy to get back to school—at least virtually 
Rick Nelson, executive editor of Evaluation Engineering, visited Keysight Technologies and had this to say about Keysight EEsof EDA.

Article 2015-09-11

 
Challenges extend from simulation to compliance 
Tami Pippert, Keysight Technologies’ high-speed digital marketing program manager, elaborates on how Keysight is enhancing its model generation, simulation, and data analysis technologies.

Article 2015-07-08

 
Improving IBIS-AMI Model Accuracy: Model-to-Model and Model-to-Lab Correlation Case Studies - Articl 
This DesignCon 2014 paper presents case studies for model-to-model & model-to-lab correlation methods & compares favorable/unfavorable factors for both methods. 10G, 11.5G and 23G SerDes data are used as examples.

Article 2015-04-02

PDF PDF 3.34 MB
Modeling, Extraction and Verification of VCSEL Model for Optical IBIS AMI 
A technique of modeling and extraction of VCSEL devices for IBIS-AMI has been proposed.

Article 2014-08-04

PDF PDF 1.18 MB
IBIS AMI Modeling of Retimer and Performance Analysis of Retimer based Active Serial Links 
This paper presents a novel retimer modeling approach based on IBIS-AMI to capture the performance of a retimer that operates up to 15 Gbps.

Article 2014-08-04

PDF PDF 1.88 MB
De-Mystifying the 28 Gb/s PCB Channel: Design to Measurement 
This paper demonstrates a design methodology for 28 Gb/s SERDES channels using Xilinx Virtex-7 Tx to show the required trade-offs that enable robust performance that is easy to verify with measurement.

Article 2014-08-04

PDF PDF 2.84 MB
Touchstone v2.0 SI/PI S-Parameter Models for Simultaneous Switching Noise (SSN) Analysis of DDR4 
This article reprint presents a methodology to setup and analyze Simultaneous Switching Noise for DDR4 applications using Touchstone v2.0 models.

Article 2014-08-04

PDF PDF 8.20 MB
Mechanism of Jitter Amplification in Clock Channels 
In this paper. jitter amplification in clock channels is analyzed analytically using the techniques developed in "Frequency domain analysis of jitter amplification in clock channels."

Article 2014-08-04

PDF PDF 715 KB
Practical Analysis of Backplane Vias - White Paper 
This paper describes the methodology of using measurements on a test vehicle to build a high bandwidth, scalable model of long vias which includes the through and stub effects which can be used for system simulation.

Case Study 2014-07-31

PDF PDF 4.57 MB
Jitter Analysis: The Dual-Dirac Model, RJ/DJ, and Q-Scale - Application Note 
This paper provides a complete description of the dual-Dirac model, how it is used in technology standards and a summary of how it is applied on different types of test equipment.

Article 2014-06-14

PDF PDF 515 KB

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