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Digital Design & Interconnect Standards

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In digital standards, every generational change puts new risks in your path. We see it first hand when creating our products and working with engineers like you. Keysight’s solution set for high-speed digital test is a combination of instrumentation and broad expertise built on our ongoing involvement with industry experts. By sharing our latest experiences, we can help anticipate challenges and accelerate your ability to create products you’ll be proud of.

Keysight - Insights for your best design

Achieve signal integrity in high-speed design with these useful tools, demos, videos and more . Learn more about Digital Design & Interconnect solutions from Keysight. 
 

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Overcome Signal Integrity Challenges in the multigigabit(s) Era 
When digital signals reach gigabit/s speeds, the unpredictable becomes the norm. The process of getting your project back on track starts with the best tools for the job.

Seminar Materials 2011-12-15

PDF PDF 781 KB
Overcoming MIPI M-PHY Protocol Layer Test Challenges Webcast 
Live broadcast August 26, 2014; 10am PT / 1pm ET

Webcast

 
Overcoming Return-Path-Discontinuity in DDR3 and GDDR5 Memory-Controller Packages 
A day in the life of a Memory Architect.

Seminar Materials 2011-10-24

PDF PDF 1.86 MB
PAM-4 Solutions for Transmit and Receive Design Characterization 
Live broadcast October 23, 2014; 10am PT / 1pm ET

Webcast

 
PCI Express 3.0 Compliance - Successfully Navigating the Standard Webcast 
Original broadcast May 7, 2013

Webcast - recorded

 
PCI Express 3.0 Receiver test of ASICs- how to face this challenge - webcast 
When PCIe 3.0 was generated, it was a goal to re-use the existing passive infrastructure - the channels. With nearly double the signal rate (8Gb/s vs. 5Gb/s), the error free transmission now heavily depends on the RX. Therefore it is now normati...

Webcast - recorded

 
Physical Layer design challenges for PCI Express® 3.0 and 2.0 designs 
You will learn advanced techniques for PCI Express phy-layer validation covering the latest PCIe 3.0 specification requirements as well as practical extensions to PCIe 2.0 and 1.1 designs. This seminar analyzes transmitter and receiver performance.

Webcast - recorded

 
Primer: A Day in the Life of your Cell Phone 
Original broadcast July 24, 2014

Webcast - recorded

 
See the Future of Oscilloscopes without Leaving your Desk 
Original broadcast October 15, 2014

Webcast - recorded

 
See the New Infiniium S-Series Oscilloscope in this 30 Minute Webcast 
Live broadcast Ocotber 22, 2014; 10am PT / 1pm ET

Webcast

 
SFP+ and 10GBASE-KR Transmitter Compliance Testing using an Oscilloscope Webcast 
Original broadcast February 19, 2014

Webcast - recorded

 
Signal Integrity Design Using Channel Simulation and EM Co-design 
The materials in this self-guided workshop will show you the “what if” design space exploration workflow that our new statistical eye diagram channel simulator enables

Seminar Materials 2010-04-21

 
Signal Integrity eSeminar Series Q&A: Being Successful with Fully Buffered DIMM (FBD) Designs 
The following Questions and Answers were created from the live eSeminar broadcast of January 25, 2005. You can view the archived eSeminar by going to

Seminar Materials 2005-01-25

PDF PDF 60 KB
Signal Integrity: Include Post-layout PCB Artwork into your Eye Diagram and BER Contour Simulation 
Originally broadcast May 5, 2010. Part of the Series: Signal Integrity for High Speed Digital Interconnects.

Webcast - recorded

 
Simulation-Measurement Workflow for DDR Compliance Webcast 
Original broadcast March 27, 2014

Webcast - recorded

 
Simultaneous Switching Noise Analysis in DDR4 applications using Power-Aware IBIS Models Webcast 
Original broadcast May 22, 2014

Webcast - recorded

 
Solving New High-Speed Design Challenges with ADS 2013.06 
In this seminar, leading Agilent EEsof R&D Designers provide a first-hand look at the new HSD features for the world class ADS transient and channel convolution simulators.

Seminar Materials 2013-07-10

 
Solving Real World Jitter Problems for High-Speed Communications eSeminar FAQs 
FAQs from the eSeminar

Seminar Materials 2006-05-11

PDF PDF 53 KB
Successful High Speed Digital Design with ADS, EMPro, and SystemVue 
The materials in this self-guided workshop will show you the latest high speed digital capabilites in ADS 2011.

Seminar Materials 2011-09-29

 
Successful High-Speed Digital Design for PC board using ADS 
A hands-on workshop on how to solve increasingly difficult signal integrity and power integrity challenges using Advanced Design System.

Seminar Materials 2014-02-27

 
SuperSpeed USB 10 Gbps (USB 3.1) Physical Layer Test Challenges Webcast 
Live broadcast Ocotber 30, 2014; 10am PT / 1pm ET

Webcast

 
Surmounting the Challenges of 16 Gigabit Operation with PCI Express Seminar 
Santa Clara, CA - October 9, 2014

Seminar

 
Surmounting the Challenges of 16 Gigabit Operation with PCI Express Webcast 
Original broadcast Ocotber 1, 2014

Webcast - recorded

 
Switch Mode Power Supply Measurements using Oscilloscopes 
Live broadcast November 18, 2014; 10am PT / 1pm ET

Webcast

 
Switching Solution Webcast 
Original broadcast December 16, 2013

Webcast - recorded

 

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