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High-Speed Digital Analysis

Perform detailed characterization with powerful analysis tools

Most serial data links begin and end with high-speed ICs designed for standards-compliant interoperability. As bit rates increase, the margins for jitter, interference and other imperfections make it increasingly difficult to achieve BER of less than 10-12. The following tools will help you characterize and analyze your designs in detail. Keysight - achieve your best design.

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Measuring Jitter in Digital Systems (AN 1448-1) - Application Brief 
This application note is for R&D designers and engineers working on high-speed digital designs. It addresses jitter measurements in digital circuits, how the different measurement techniques are best applied, and how these decisions may change as the data rates increase.

Application Note 2013-09-16

PDF PDF 1.78 MB
DDR4 TdiVW/VdiVW Bit Error Rate Measurement or Understanding Bit Error Rate 
Importance of making BER measurement calculations to form a statistical measurement of total jitter to understand the design's data valid window result and design error rates.

Application Note 2013-01-24

PDF PDF 1.65 MB
Effective Reflection Characterization for Active Devices Using ENA Option TDR Application Note 
This application note describes Hot TDR measurement, which is an effective characterization method for the reflection of transmitter and receiver.

Application Note 2012-01-12

N4916B De-emphasis Signal Converter Data Sheet 
The N4916B de-emphasis signal converter enables R&D and test engineers to accurately characterize gigabit serial ports and channels. The clock doubler option is needed to analyze half-rate clock devices.

Data Sheet 2011-04-13

PDF PDF 3.07 MB
Forward Clocking - Receiver (RX) Jitter Tolerance Test with J-BERT N4903B High-P - Application Note 
This document describes the requirements for forward clocking topology RX Jitter tolerance testing.

Application Note 2009-03-24

PDF PDF 606 KB
Characterizing Clock Jitter through Phase Noise Measurements Speeds up Design Verification Process 
This white paper discusses a new measurement method for obtaining highly accurate low random jitter (RJ) measurements and performing real-time analysis of RJ and periodic jitter (PJ) of components.

Application Note 2008-11-20

Jitter Solutions for Telecom, Enterprise, and Digital Designs - Brochure 
Complete solutions for characterization and test of jitter in high-speed digital transmission systems, high-speed I/O connections, and buses.

Brochure 2008-06-25

PDF PDF 3.49 MB
Complete solutions for characterization, debug, compliance test of HDMI designs - Brochure 
This brochure discusses test solutions for HDMI. Thorough characterization and validation of HDMI-based designs

Brochure 2007-10-19

PDF PDF 1.12 MB
How to characterize the Physical Layer of the Mobile Industry Processor Interface (MIPI D-PHY) 
How to characterize the Physical Layer of the Mobile Industry Processor Interface (MIPI D-PHY)

Application Note 2007-07-30

PDF PDF 611 KB
Using Receiver Tolerance Testing to Assess the Performance of High-Speed Devices - App Note 
Using Receiver Tolerance Testing to Assess the Performance of High-Speed Devices

Application Note 2007-06-19

PDF PDF 214 KB
Precision Jitter Analysis Using the Keysight 86100C DCA-J (PN 86100C-1) 
This product note provides a guide to making jitter measurements with the Keysight 86100C DCA-J.

Application Note 2007-03-07

Automated USB 2.0 Receiver Compliance Test and Characterization with the Keysight N5990A - App Note 
Automated USB 2.0 Receiver Compliance Test and Characterization with the Keysight N5990A Software Platform: 8 pages

Application Note 2007-01-31

PDF PDF 272 KB
Simulation of Jittering Synchronization Signals for Video Interfaces (PN 4) - Application Note 
This Product Note shows how Research and Development engineers use pulse generators of the Keysight 81100 Family for the development of interfaces ...

Application Note 2006-12-12

PDF PDF 382 KB
Using Clock Jitter Analysis to Reduce BER in Serial Data Applications 
This Application Note emphasizes on the emerging techniques for reference clock jitter analysis from the perspective of oscillator physics, phase noise theory, and serial data technology.

Application Note 2006-12-01

HDMI Sink and Source Compliance Test and Characterization - Application Note 
In this product note examples are given for advanced, automated HDMI compliance tests and characterization based on a high bandwidth oscilloscope, a TMDS Signal Generator and the Test Automation Software Platform.

Application Note 2006-10-27

Automated PCI Express Receiver Compliance Test and Characterization with N5990A - Application Note 
This product note shows how to use the test automation software platform to verify and debug your PCI Express bus designs. As an example, a multi-lane add-in card is used.

Application Note 2006-08-29

PDF PDF 444 KB
Calibrated Jitter, Jitter Tolerance Test and Jitter Laboratory with J-BERT N4903A - App Note 
This application note describes the N4903A BERT characterization solution for emerging serial gigabit devices: it helps engineers make quick and accurate jitter tolerance tests, which have been complicated and hard to do in the past.

Application Note 2006-07-18

PDF PDF 5.33 MB
Mastering Jitter in Serial Gigabit Designs - Brochure 
Mastering Jitter in Serial Gigabit Designs

Promotional Materials 2006-06-22

PDF PDF 1.01 MB
Comparison of Different Jitter Analysis Techniques With a Precision Transmitter 
This white paper describes how various jitter analysis techniques give dissimilar results. Which is right? We built a precision jitter transmitter to compare results of different techniques where test sets were exposed to known levels of jitter.

Application Note 2006-04-06

PDF PDF 164 KB
Advanced Memory Buffer (AMB), Characterization of Timing and Voltage Specification 
Advanced Memory Buffer (AMB), Characterization of Timing and Voltage Specification

Application Note 2005-09-22

PDF PDF 812 KB
Eye Characterization on Idle and Framed Data Traffic: the Bit Recovery Mode - Application Note 
Traditionally, bit error rate testing compares the bits from a Device Under Test (DUT) against a reference data set, called the expected data. The user of Bit Error Ratio Tester (BERT) has to provide this expected data and load it into the tester.

Application Note 2005-09-21

PDF PDF 356 KB
Improved Method for Characterizing and Modeling Gigabit Flex-Circuit Based Interconnects 
This paper describes sophisticated, time-domain methods of accurately predicting time- and frequency-domain high-speed signal characteristics.

Application Note 2005-09-08

PDF PDF 11.72 MB
Fast Total Jitter Test Solution - Application Note 
This application note compares different total jitter measurement and extrapolation techniques to the Fast Total Jitter Measurement

Application Note 2005-08-29

PDF PDF 1.28 MB
Total Jitter Measurements at Low Probability Levels, Using Optimized BERT Scan Method 
This paper describes an optimized technique based on probabliity and statistics theory that enables accurate TJ measurements at the 1e-12 bit error ratio level in about 20 minutes at 10 Gbit/s.

Application Note 2005-07-11

PDF PDF 894 KB
Total Jitter Measurement at Low Probability Levels 
White paper produced for DesignCon 2005 regarding Total Jitter Measurement at Low Probability Levels, Using Optimized BERT Scan Method.

Application Note 2005-07-11

PDF PDF 222 KB

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