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高速デジタル・デザインの問題

  • 個々のコンポーネントを適切な抽象化レベル(チャネル/回路/物理レベル)でコ・シミュレートすることにより、正確なチップ間リンクを解析
  • バックプレーンのSパラメータ・モデルの回路/チャネル・シミュレーションへの正確なインポートによる、因果律/受動性の回避
  • シミュレーションによる測定プレーン間の補間/仮想プロトタイプへの外挿前の、測定データとシミュレーション・データの相関

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Sパラメータ・モデルを使用したFPGAのパワー・インテグリティ・シミュレーション 
Sパラメータ・モデルを使用したFPGAのパワー・インテグリティ・シミュレーション

アプリケーション・ノート 2014-12-12

Keysight Donates $120 Mil. Gift of Software, Support and Training to Georgia Institute of Technology 
Keysight announces the largest in-kind software donation in its longstanding relationship with the Georgia Institute of Technology.

プレス資料 2014-12-10

 
Keysight Receives Global Frost & Sullivan Award for Market Leadership in Instrumentation Software 
Keysight Technologies announces that Frost & Sullivan has recognized Keysight with the 2014 Global Frost & Sullivan Award for Market Leadership in Instrumentation Software for excellence in capturing the highest market revenue within its industry. The award is based on Frost & Sullivan's recent analysis of the instrumentation software market.

プレス資料 2014-12-08

 
Keysight to Demonstrate Hardware and Electronic Design Automation Software Solutions at EPEPS 2014 
Keysight Technologies announces it will demonstrate its latest hardware and electronic design automation software solution releases at EPEPS 2014, Embassy Suites Portland, Portland, Oregon, Oct. 26-29. Keysight is a silver-level sponsor of the event.

プレス資料 2014-10-23

 
Design Challenges in DDR4 - The Keysight DDR Bus Simulator 
This video is about design challenges in DDR4 and in particular the DDR Bus Simulator, which is a new Keysight EEsof EDA simulation tool for DDR4 and beyond.

デモ 2014-10-16

 
Keysight Technologies Demonstrates Simulation, Debug, Validation and Test Solutions at MemCon 
Keysight announces it will demonstrate solutions that provide simulation, debug, validation and test for the fastest speed memory designs at MemCon, Santa Clara Convention Center, Booth102, Santa Clara, Calif., Oct. 15.

プレス資料 2014-10-13

 
Keysight Technologies High Speed Digital Design with Advanced Design System 
Keysight EEsof EDAでは長年、RF/マイクロ波の優れたシミュレータとしてAdvanced Design System(ADS)を提供しています。ADSは、RF/マイクロ波エンジニアリングでの回路解析や高周波での信号障害の解決に広く使用されています。現在Keysight EEsof EDAでは、適切なシミュレータ、ライブラリ、機能を3つのADSバンドルとして提供しています。

ブローシャ 2014-10-07

PDF PDF 2.31 MB
DDR Compliance Integration with Advanced Design System 
The W2351EP DDR4 Compliance Test Bench helps solve the problem of simulation-measurement correlation.

デモ 2014-10-03

 
DDR Memory Test Solutions Overview 
This video provides an overview of Keysight's DDR Memory test solutions, from simulation, transmitter compliance, protocol, and probing solutions.

デモ 2014-10-03

 
Keysight Introduces DDR Bus Simulator to Solve the Bit-Error-Rate Contour Simulation Challenge 
Keysight Technologies introduces the DDR Bus Simulator; the industry’s first tool to generate accurate Bit-Error-Rate (BER) contours for the JEDEC DDR memory bus specification.

プレス資料 2014-09-30

 
High Speed Digital Design and Simulation Videos on YouTube 
Keysight EEsof EDA's High Speed Digital Design and Simulation video playlist on YouTube.

デモ 2014-08-06

 
ADS Videos on YouTube 
Advanced Design System (ADS) Video Library playlist in Keysight EEsof EDA's Channel on YouTube

デモ 2014-08-06

 
Mechanism of Jitter Amplification in Clock Channels 
In this paper. jitter amplification in clock channels is analyzed analytically using the techniques developed in "Frequency domain analysis of jitter amplification in clock channels."

記事 2014-08-04

PDF PDF 715 KB
Quick Start for Signal Integrity Design Using Advanced Design System (ADS) – Technical Overview 
This demo guide is a part of the high-speed digital design workflow for signal integrity engineers using Advanced Design System.

技術概要 2014-08-04

PDF PDF 3.82 MB
IBIS AMI Modeling of Retimer and Performance Analysis of Retimer based Active Serial Links 
This paper presents a novel retimer modeling approach based on IBIS-AMI to capture the performance of a retimer that operates up to 15 Gbps.

記事 2014-08-04

PDF PDF 1.88 MB
De-Mystifying the 28 Gb/s PCB Channel: Design to Measurement 
This paper demonstrates a design methodology for 28 Gb/s SERDES channels using Xilinx Virtex-7 Tx to show the required trade-offs that enable robust performance that is easy to verify with measurement.

記事 2014-08-04

PDF PDF 2.86 MB
Modeling, Extraction and Verification of VCSEL Model for Optical IBIS AMI 
A technique of modeling and extraction of VCSEL devices for IBIS-AMI has been proposed.

記事 2014-08-04

PDF PDF 1.18 MB
Improving IBIS-AMI Model Accuracy: Model-to-Model and Model-to-Lab Correlation Case Studies 
This paper presents case studies for model-to-model & model-to-lab correlation methods & compares favorable/unfavorable factors for both methods. 10G, 11.5G and 23G SerDes data are used as examples.

記事 2014-08-04

PDF PDF 3.32 MB
Analysis of Test Coupon Structures for the Extraction of High Frequency PCB Material Properties 
Exploration of the addition of Beatty series resonant impedance structures to improve the accuracy of extracting PCB material properties for the purpose of constructing 3D-EM simulations.

アプリケーション・ノート 2014-08-03

PDF PDF 2.19 MB
RF and Microwave Industry-Ready Student Certification Program - Brochure 
This program confirms a student’s technical knowledge, design expertise, and hands-on measurement proficiency in the use of Keysight EEsof software design tools and Keysight instruments.

ブローシャ 2014-08-03

PDF PDF 562 KB
EDA Support Services - Flyer 
Keysight Support Services for EDA Products offers customers several benefits otherwise not available. This service is designed to help you get the most out of your software purchases.

ブローシャ 2014-08-03

PDF PDF 454 KB
Keysight EEsof EDA Software and Modular Solutions for Universities 
Keysight works in collaboration with universities to provide tools that enable education and research for the engineers of tomorrow. The brochure outlines available programs, software and hardware.

ブローシャ 2014-08-03

PDF PDF 1.44 MB
Controlled Impedance Line Designer in ADS 
The Controlled Impedance Line Designer in ADS enables signal integrity engineers to do pre-layout controlled impedance line design by optimizing the substrate stack up and the transmission line geometry.

デモ 2014-08-01

 
New ADS DDR4 Compliance Test Bench for Solving the Simulation-Measurement Correlation Challenge 
Agilent introduces Advanced Design System DDR4 Compliance Test Bench, which enables a complete workflow for DDR4 engineers from simulation of a candidate design through measurement of the finished prototype. The solution is ideal for semiconductor companies developing DDR controller IP; those developing DRAM chips and DIMMs; and OEMs integrating the controller and DIMM into a system using PCB technology.

プレス資料 2014-06-30

 
Discovering ADS 
A collection of Keysight EEsof EDA ADS video demonstrations and tutorials

デモ 2014-03-20

 

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