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DDR Memory Design & Test

Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) is implemented in several forms today:

  • DDR, DDR1, DDR2, DDR3, DDR4 – advancing generations of DDR technology with progressively faster data rates and clock frequencies
  • LPDDR, LPDDR2, LPDDR3, LPDDR4 – generations of low-power DDR targeted for mobile devices
  • GDDR5 – graphical DDR targeted for graphics boards
  • UFS – universal flash storage, the next generation of mobile storage

Keysight’s solutions for DDR memory applications are driven and supported by Keysight experts that are active in the Joint Electronic Devices Engineering Council (JEDEC). Our involvement in standards groups and their related workshops, and specification development enables Keysight to bring the right solutions to the market when our customers need them.

Regardless of the DDR generation design challenges you are facing, Keysight offers a complete solution set from electrical to protocol. Work with Keysight and gain insights for your best design.

See measurement solution examples to discover specific solutions for your DDR and memory needs.
 

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DDR4 Protocol Analysis - FuturePlus 
DDR4 Protocol Analysis from FuturePlus and Keysight.

Brève de solutions 2014-04-29

 
Tips for Making Better Memory Measurements – Video Series 
Videos that show customers how perform a comprehensive, unique and extensive analysis in less time.

Demo 2013-03-18

 
DDR4 TdiVW/VdiVW Bit Error Rate Measurement or Understanding Bit Error Rate 
Importance of making BER measurement calculations to form a statistical measurement of total jitter to understand the design's data valid window result and design error rates.

Application Note 2013-01-24

PDF PDF 1.65 MB
DDR Memory Design and Test – A Better Way 
Keysight offers the complete solutions for all areas of DDR design, meeting your needs for electrical physical layer, protocol layer, and functional test.

Brochure 2012-12-19

PDF PDF 5.17 MB
DDR Memory Design and Test Overview  
Brief overview of Keysight solutions for DDR design and test.

Brochure 2012-12-19

PDF PDF 1.14 MB
DDR Memory Overview, Development Cycle, and Challenges - Technical Overview 
Thanks to improved manufacturing processes that have driven down costs, the technology of choice is now DDR SDRAM, short for Double Data Rate Synchronous Dynamic Random Access Memory.

Application Note 2012-12-14

PDF PDF 1.37 MB
B4621B for DDR2, DDR3, or DDR4 Debug and Validation - Data Sheet 
The B4621B protocol-decode software translates Translates acquired signals into easily understood bus transactions showing associated data bursts for double- edge data-rate captures up to 2.5Gb/s.

Data Sheet 2012-09-04

PDF PDF 1.32 MB
B4623B Bus Decoder for LPDDR, LPDDR2, or LPDDR3 Debug and Validation - Data Sheet 
The B4623B protocol-decode software translates Translates acquired signals into easily understood bus transactions showing associated data bursts for LPDDR, LPDDR2, LPDDR3 at full bus data rates.

Data Sheet 2012-09-03

PDF PDF 1.03 MB
Crossing the Digital-Analog Divide - White Paper 
This white paper helps to better understand how to cope with the physical nature of signals that we might prefer to think of as bits, nibbles and bytes, let's start with an ideal digital waveform.

Application Note 2012-05-02

PDF PDF 6.46 MB
Maximizing DDR BGA probe Bandwidth for Superior Signal Fidelity 
The use of BGA probes for probing DDR DRAM is becoming more popular and almost a requirement as memory design gets more complex and compact and data rate gets higher. DDR3 and DDR4 data rate is increasing from 800MT/s to possibly 3200MT/s.

Application Note 2012-01-31

PDF PDF 1.40 MB
Agilent Technologies Introduces Industry's Fastest Logic Analyzer  
New Instrument Offers Reliable Data Capture Rates up to 4 Gb/s on Industry's Smallest Eye Openings

Press Materials 2011-03-28

 
Ensuring Compliance and Interoperability of DDR Designs 
The Joint Electronic Devices Engineering Council (JEDEC) specification requires a large number of test parameters to be verified for DDR compliance – a time-consuming exercise if you make the measurements manually.

Application Note 2008-12-19

PDF PDF 379 KB
DDR Probing for Physical Layer and Functional Testing 
Probing is the key to accessing signals and validating your designs. Although you may normally probe at signal vias or designed-in probe points, for DDR these do not always provide good signal integrity.

Application Note 2008-12-19

PDF PDF 617 KB
Separating Read/Write Signals for DDR DRAM and Controller Validation 
To analyze the signal integrity of DDR signals, you need to differentiate the complex traffic on the data bus to independently analyze the signal performance for both DDR chip and memory controller.

Application Note 2008-12-19

PDF PDF 805 KB
Find and identify the causes of data corruption and elusive failures 
The Protocol-decode software allows you to track and fix infrequent glitches and other signal anomalies that might otherwise be difficult to find.

Application Note 2008-12-19

PDF PDF 360 KB
Debugging Signal Integrity and Protocol Layers on DDR Designs 
As DDR data transmission rates increase, signal integrity and clarity become critical concerns. So one of the primary challenges with DDR is debugging failures.

Application Note 2008-12-19

PDF PDF 984 KB
A Time-Saving Method for Analyzing Signal Integrity in DDR Memory Buses 
This application note covers new tools and measurement techniques for characterizing and validating signal integrity of DDR (double data rate synchronous dynamic random access memory) signals.

Application Note 2008-09-10

Jitter Solutions for Telecom, Enterprise, and Digital Designs - Brochure 
Complete solutions for characterization and test of jitter in high-speed digital transmission systems, high-speed I/O connections, and buses.

Brochure 2008-06-25

PDF PDF 3.49 MB
DDR 1, 2 and 3 solutions Video 
Includes probing methods, read/write separation technique and automated JEDEC compliance measurements with Infiniium Series oscilloscopes.

Demo 2007-12-27

WMF WMF 52.75 KB
Improve Your Time-to-Insight:Debugging Intermittent Memory Failures in DDR and DDR2 Systems 
Application Note 1575

Application Note 2006-04-14

Probe loading 
Probe loading

Demo 2005-12-22

WMF WMF 19.66 MB
Flexibility of Keysight's InfiniiMax Probe System 
This 10-minute video provides some very practical

Product Tour 2004-11-22

WMF WMF 27.29 MB
Designing and Validating High-Speed Memory Buses (AN 1382-2) 
DDR SDRAM (double data rate synchronous dynamic random access memory) is quickly becoming an accepted technology in the PC (personal computer) industry. Its low cost, high performance, and increasingly wide availability make it very desirable for PC memory buses and embedded designs such as high...

Application Note 2001-12-20