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DDR 存储器设计和测试

双数据速率(DDR)同步动态随机存取存储器(SDRAM)现在有多种形式,其中包括最原始的 DDR(也称为 DDR1);性能更高、功耗更低的 DDR2;具有更佳性能的 DDR3;以及面向移动器件的低功率 DDR (LPDDR)。

是德是 JEDEC 的积极成员,一直以来都在积极参与研讨会和相关标准等问题。您在此找到的这些资源将使您能够概括地认识 DDR 设计,帮助您了解最新的测量技术,并为您讲解设计和调试方法。

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DDR4 Protocol Analysis - FuturePlus 
DDR4 Protocol Analysis from FuturePlus and Keysight.

Solution Brief 2014-04-29

 
Tips for Making Better Memory Measurements – Video Series 
Videos that show customers how perform a comprehensive, unique and extensive analysis in less time.

基本演示 2013-03-18

 
DDR4 TdiVW/VdiVW Bit Error Rate Measurement or Understanding Bit Error Rate 
Importance of making BER measurement calculations to form a statistical measurement of total jitter to understand the design's data valid window result and design error rates.

应用说明 2013-01-24

PDF PDF 1.65 MB
DDR Memory Design and Test – A Better Way 
Keysight offers the complete solutions for all areas of DDR design, meeting your needs for electrical physical layer, protocol layer, and functional test.

手册 2012-12-19

PDF PDF 5.17 MB
DDR Memory Design and Test Overview  
Brief overview of Keysight solutions for DDR design and test.

手册 2012-12-19

PDF PDF 1.14 MB
DDR Memory Overview, Development Cycle, and Challenges - Technical Overview 
Thanks to improved manufacturing processes that have driven down costs, the technology of choice is now DDR SDRAM, short for Double Data Rate Synchronous Dynamic Random Access Memory.

应用说明 2012-12-14

PDF PDF 1.37 MB
B4621B for DDR2, DDR3, or DDR4 Debug and Validation - Data Sheet 
The B4621B protocol-decode software translates Translates acquired signals into easily understood bus transactions showing associated data bursts for double- edge data-rate captures up to 2.5Gb/s.

产品资料 2012-09-04

PDF PDF 1.32 MB
B4623B Bus Decoder for LPDDR, LPDDR2, or LPDDR3 Debug and Validation - Data Sheet 
The B4623B protocol-decode software translates Translates acquired signals into easily understood bus transactions showing associated data bursts for LPDDR, LPDDR2, LPDDR3 at full bus data rates.

产品资料 2012-09-03

PDF PDF 1.03 MB
Crossing the Digital-Analog Divide - White Paper 
This white paper helps to better understand how to cope with the physical nature of signals that we might prefer to think of as bits, nibbles and bytes, let's start with an ideal digital waveform.

应用说明 2012-05-02

PDF PDF 6.46 MB
Maximizing DDR BGA probe Bandwidth for Superior Signal Fidelity 
The use of BGA probes for probing DDR DRAM is becoming more popular and almost a requirement as memory design gets more complex and compact and data rate gets higher. DDR3 and DDR4 data rate is increasing from 800MT/s to possibly 3200MT/s.

应用说明 2012-01-31

PDF PDF 1.40 MB
Agilent Technologies Introduces Industry's Fastest Logic Analyzer  
New Instrument Offers Reliable Data Capture Rates up to 4 Gb/s on Industry's Smallest Eye Openings

新闻资料 2011-03-28

 
Find and identify the causes of data corruption and elusive failures 
The Protocol-decode software allows you to track and fix infrequent glitches and other signal anomalies that might otherwise be difficult to find.

应用说明 2008-12-19

PDF PDF 360 KB
Ensuring Compliance and Interoperability of DDR Designs 
The Joint Electronic Devices Engineering Council (JEDEC) specification requires a large number of test parameters to be verified for DDR compliance – a time-consuming exercise if you make the measurements manually.

应用说明 2008-12-19

PDF PDF 379 KB
Debugging Signal Integrity and Protocol Layers on DDR Designs 
As DDR data transmission rates increase, signal integrity and clarity become critical concerns. So one of the primary challenges with DDR is debugging failures.

应用说明 2008-12-19

PDF PDF 984 KB
Separating Read/Write Signals for DDR DRAM and Controller Validation 
To analyze the signal integrity of DDR signals, you need to differentiate the complex traffic on the data bus to independently analyze the signal performance for both DDR chip and memory controller.

应用说明 2008-12-19

PDF PDF 805 KB
DDR Probing for Physical Layer and Functional Testing 
Probing is the key to accessing signals and validating your designs. Although you may normally probe at signal vias or designed-in probe points, for DDR these do not always provide good signal integrity.

应用说明 2008-12-19

PDF PDF 617 KB
A Time-Saving Method for Analyzing Signal Integrity in DDR Memory Buses 
This application note covers new tools and measurement techniques for characterizing and validating signal integrity of DDR (double data rate synchronous dynamic random access memory) signals.

应用说明 2008-09-10

适用于电信、企业和数字设计的抖动解决方案 
Complete solutions for characterization and test of jitter in high-speed digital transmission systems, high-speed I/O connections, and buses.

手册 2008-06-25

PDF PDF 3.49 MB
Jitter Solutions for Telecom, Enterprise, and Digital Designs - Brochure 
Complete solutions for characterization and test of jitter in high-speed digital transmission systems, high-speed I/O connections, and buses.

手册 2008-06-25

PDF PDF 3.49 MB
DDR 1, 2 and 3 solutions Video 
Includes probing methods, read/write separation technique and automated JEDEC compliance measurements with Infiniium Series oscilloscopes.

基本演示 2007-12-27

WMF WMF 52.75 KB
改善查看周期:调试DDR和DD2系统中的间歇 

应用说明 2006-05-01

Probe loading 
Probe loading

基本演示 2005-12-22

WMF WMF 19.66 MB
Flexibility of Keysight's InfiniiMax Probe System 
This 10-minute video provides some very practical

产品展示 2004-11-22

WMF WMF 27.29 MB
Designing and Validating High-Speed Memory Buses (AN 1382-2) 
DDR SDRAM (double data rate synchronous dynamic random access memory) is quickly becoming an accepted technology in the PC (personal computer) industry. Its low cost, high performance, and increasingly wide availability make it very desirable for PC memory buses and embedded designs such as high...

应用说明 2001-12-20