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DDR Memory Design & Test

Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) is implemented in several forms today:

  • DDR, DDR1, DDR2, DDR3, DDR4 – advancing generations of DDR technology with progressively faster data rates and clock frequencies
  • LPDDR, LPDDR2, LPDDR3, LPDDR4 – generations of low-power DDR targeted for mobile devices
  • GDDR5 – graphical DDR targeted for graphics boards
  • UFS – universal flash storage, the next generation of mobile storage

Keysight’s solutions for DDR memory applications are driven and supported by Keysight experts that are active in the Joint Electronic Devices Engineering Council (JEDEC). Our involvement in standards groups and their related workshops, and specification development enables Keysight to bring the right solutions to the market when our customers need them.

Regardless of the DDR generation design challenges you are facing, Keysight offers a complete solution set from electrical to protocol. Work with Keysight and gain insights for your best design.

See measurement solution examples to discover specific solutions for your DDR and memory needs.
 

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Accelerate DDR4/LPDDR3 Memory Debug with Bus level Signal Integrity Insight Webcast 
Original broadcast March 4, 2014

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Accelerate FPGA Debug by Applying Latest Tools and Methods Webcast 
Original broadcast June 10, 2014

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Common DFT guidelines for implementing boundary scan on limited access boards webcast 
Original broadcast September 11, 2014

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Extending boundary scan tests to improve test coverage of limited access boards webcast 
Original broadcast September 25, 2014

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Fixture De-embedding Techniques for 28 Gb/s Transmitter Measurements Webcast 
Live broadcast January 23, 2014; 10am PT/1pm ET/19:00 CET

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Fixturing and Fixture Removal for Multiport Devices with Non-Standard RF Interfaces Webcast 
Original broadcast March 11, 2014

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How to Optimize Your SerDes Design During the Pre-layout Phase Webcast 
Original broadcast September 25, 2014

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Introduction to the Keysight x1149 Boundary Scan Analyzer Webcast 
Original broadcast August 26, 2014; 9am PT / 12pm ET

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Maximizing test coverage of multiple limited access boards by linking multiple boundary scan chains 
Original broadcast October 9, 2014

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New Calibration Method Simplifies Measurements of Fixtured Devices Webcast 
Original broadcast July 29, 2014

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Next generation BERT Ensures Signal Integrity in High-speed Digital Designs Webcast 
Original broadcast January 21, 2014

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Simulation-Measurement Workflow for DDR Compliance Webcast 
Original broadcast March 27, 2014

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Simultaneous Switching Noise Analysis in DDR4 applications using Power-Aware IBIS Models Webcast 
Original broadcast May 22, 2014

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Using Logic Analysis to Find Root Cause of Digital Design Errors Webcast 
Recorded broadcast December 17, 2013

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