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DDR Memory Design & Test

Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) is implemented in several forms today – the original DDR (also called DDR1), DDR2 which improved performance and lowered power consumption, DDR3 with even better performance, and low-power DDR (LPDDR), that is targeted for mobile devices.

Keysight is an active member of JEDEC, with consistent participation in workshops and specification issues. These resources you find here will provide you with an overview of DDR design, understand the latest measurement techniques, and illustrate design and debug approaches.

Use the matrix below to discover specific solutions for your DDR needs.

  Simulation Parametric Test (Oscilloscope) Functional Validation (Logic Analyzers) Probing Solutions
DDR2 W2302EP                N5413B                B4622B       W2633B
DDR3 W2302EP                U7231B                B4622B       W3631A
DDR4   Planned                N6462A                B4622B  
LPDDR2 LPDDR2                N5413B                B4622B  
LPDDR3   Planned                U7231B                B4622B  
GDDRS   Planned                U7245A    
UFS                  N8818A    

Explore YouTube Videos 

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Accelerate DDR4/LPDDR3 Memory Debug with Bus level Signal Integrity Insight Webcast 
Original broadcast March 4, 2014

Webcast - recorded

Accelerate FPGA Debug by Applying Latest Tools and Methods Webcast 
Original broadcast June 10, 2014

Webcast - recorded

DesignCon 2014 
Jan 28-31, 2014; Santa Clara Convention Center Download papers presented, order the AEF DVD


Next generation BERT Ensures Signal Integrity in High-speed Digital Designs Webcast 
Original broadcast January 21, 2014

Webcast - recorded

Using Logic Analysis to Find Root Cause of Digital Design Errors Webcast 
Recorded broadcast December 17, 2013

Webcast - recorded