전문가 상담

DDR, DDR2, DDR3, DDR4 메모리 설계 및 테스트

현재, DDR(Double Data Rate) SDRAM(Synchronous Dynamic Random Access Memory)은 몇 가지 형태로 구현되고 있습니다.

키사이트의 DDR 메모리 어플리케이션용 솔루션은 JEDEC(Joint Electronic Devices Engineering Council)에서 활동하고 있는 키사이트 전문가들이 개발 및 지원합니다. 표준 그룹과 관련 워크숍에서 활발히 활동하고 사양 개발을 위해 노력하고 있는 키사이트는 고객의 요구에 부합하는 이상적인 솔루션을 출시할 수 있습니다.

고객이 직면하고 있는 DDR 설계상의 문제에 관계 없이, 키사이트는 전기부터 프로토콜에 이르기까지 완전한 솔루션 세트를 공급합니다. 키사이트와 함께 자신에게 딱 맞는 솔루션을 찾아보십시오.

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B4621B for DDR2, DDR3, or DDR4 Debug and Validation - Data Sheet 
The B4621B protocol-decode software translates Translates acquired signals into easily understood bus transactions showing associated data bursts for double- edge data-rate captures up to 2.5Gb/s.

데이터시트 2015-02-26

PDF PDF 837 KB
In-Circuit Test Suite - Brochure 
Latest board and functional test solutions to help electronics manufacturers achieve better product quality withmore comprehensive test coverage.

브로셔 2015-02-01

PDF PDF 10.42 MB
DDR4 Protocol Analysis - FuturePlus 
DDR4 Protocol Analysis from FuturePlus and Keysight.

솔루션 개요 2014-04-29

 
Tips for Making Better Memory Measurements – Video Series 
Videos that show customers how perform a comprehensive, unique and extensive analysis in less time.

기본 데모 2013-03-18

 
DDR4 TdiVW/VdiVW Bit Error Rate Measurement or Understanding Bit Error Rate 
Importance of making BER measurement calculations to form a statistical measurement of total jitter to understand the design's data valid window result and design error rates.

어플리케이션 노트 2013-01-24

PDF PDF 1.65 MB
DDR Memory Design and Test Overview  
Brief overview of Keysight solutions for DDR design and test.

브로셔 2012-12-19

PDF PDF 1.14 MB
DDR Memory Design and Test – A Better Way 
Keysight offers the complete solutions for all areas of DDR design, meeting your needs for electrical physical layer, protocol layer, and functional test.

브로셔 2012-12-19

PDF PDF 5.17 MB
DDR Memory Overview, Development Cycle, and Challenges - Technical Overview 
Thanks to improved manufacturing processes that have driven down costs, the technology of choice is now DDR SDRAM, short for Double Data Rate Synchronous Dynamic Random Access Memory.

어플리케이션 노트 2012-12-14

PDF PDF 1.37 MB
B4623B Bus Decoder for LPDDR, LPDDR2, or LPDDR3 Debug and Validation - Data Sheet 
The B4623B protocol-decode software translates Translates acquired signals into easily understood bus transactions showing associated data bursts for LPDDR, LPDDR2, LPDDR3 at full bus data rates.

데이터시트 2012-09-03

PDF PDF 1.03 MB
Crossing the Digital-Analog Divide - White Paper 
This white paper helps to better understand how to cope with the physical nature of signals that we might prefer to think of as bits, nibbles and bytes, let's start with an ideal digital waveform.

어플리케이션 노트 2012-05-02

PDF PDF 6.46 MB
Maximizing DDR BGA probe Bandwidth for Superior Signal Fidelity 
The use of BGA probes for probing DDR DRAM is becoming more popular and almost a requirement as memory design gets more complex and compact and data rate gets higher. DDR3 and DDR4 data rate is increasing from 800MT/s to possibly 3200MT/s.

어플리케이션 노트 2012-01-31

PDF PDF 1.40 MB
Agilent Technologies Introduces Industry's Fastest Logic Analyzer  
New Instrument Offers Reliable Data Capture Rates up to 4 Gb/s on Industry's Smallest Eye Openings

보도자료 2011-03-28

 
Debugging Signal Integrity and Protocol Layers on DDR Designs 
As DDR data transmission rates increase, signal integrity and clarity become critical concerns. So one of the primary challenges with DDR is debugging failures.

어플리케이션 노트 2008-12-19

PDF PDF 984 KB
Separating Read/Write Signals for DDR DRAM and Controller Validation 
To analyze the signal integrity of DDR signals, you need to differentiate the complex traffic on the data bus to independently analyze the signal performance for both DDR chip and memory controller.

어플리케이션 노트 2008-12-19

PDF PDF 805 KB
DDR Probing for Physical Layer and Functional Testing 
Probing is the key to accessing signals and validating your designs. Although you may normally probe at signal vias or designed-in probe points, for DDR these do not always provide good signal integrity.

어플리케이션 노트 2008-12-19

PDF PDF 617 KB
Find and identify the causes of data corruption and elusive failures 
The Protocol-decode software allows you to track and fix infrequent glitches and other signal anomalies that might otherwise be difficult to find.

어플리케이션 노트 2008-12-19

PDF PDF 360 KB
Ensuring Compliance and Interoperability of DDR Designs 
The Joint Electronic Devices Engineering Council (JEDEC) specification requires a large number of test parameters to be verified for DDR compliance – a time-consuming exercise if you make the measurements manually.

어플리케이션 노트 2008-12-19

PDF PDF 379 KB
A Time-Saving Method for Analyzing Signal Integrity in DDR Memory Buses 
This application note covers new tools and measurement techniques for characterizing and validating signal integrity of DDR (double data rate synchronous dynamic random access memory) signals.

어플리케이션 노트 2008-09-10

DDR 1, 2 and 3 solutions Video 
Includes probing methods, read/write separation technique and automated JEDEC compliance measurements with Infiniium Series oscilloscopes.

기본 데모 2007-12-27

WMF WMF 52.75 KB
Improve Your Time-to-Insight:Debugging Intermittent Memory Failures in DDR and DDR2 Systems 
Application Note 1575

어플리케이션 노트 2006-04-14

Probe loading 
Probe loading

기본 데모 2005-12-22

WMF WMF 19.66 MB
텔레콤, 기업 및 디지털 설계를 위한 지터 솔루션  
고속 디지털 전송 시스템, 고속 I/O 연결 및 버스에서 지터의 특성분석 및 테스트를 위한 완전한 솔루션입니다.

브로셔 2005-08-26

PDF PDF 1.38 MB
Flexibility of Keysight's InfiniiMax Probe System 
This 10-minute video provides some very practical

제품 둘러보기 2004-11-22

WMF WMF 27.29 MB
Designing and Validating High-Speed Memory Buses (AN 1382-2) 
DDR SDRAM (double data rate synchronous dynamic random access memory) is quickly becoming an accepted technology in the PC (personal computer) industry. Its low cost, high performance, and increasingly wide availability make it very desirable for PC memory buses and embedded designs such as high...

어플리케이션 노트 2001-12-20