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PCI Express® (PCIe) Design & Test

Peripheral Component Interconnect Express, officially abbreviated as PCIe® or PCI Express®, is a computer expansion bus standard designed to replace the older bus standards such as PCI. 

PCIe 2.0 doubles the transfer rate of PCIe 1.0 to 5 GT/s and the per-lane throughput rises from 250 MB/s to 500 MB/s.

PCIe 3.0 has a 8 GT/s bit rate which is backward compatible with PCIe 2.0 and effectively delivers double the PCIe 2.0 bandwidth. 

PCIe 4.0 at 16 GT/s doubles data rates again, requiring extensive testing and validation to enable speed, while maintaining backward compatibility with earlier generations.

Regardless of the generation of PCIe design you are testing or the PCI Express design challenges you are facing, Keysight offers a complete solution set from design to test. Work with Keysight and gain insights for you best PCIe design.


Keysight RF and Digital Learning Center - A commitment to learning with industry experts

See measurement solution examples to discover specific solutions for your PCIe needs

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Extreme Oscilloscope Probing Challenges and Solutions Webcast 
Original broadcast February 16, 2017

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USB Type-C Design Implementations – Overcoming Test Challenges 
Original broadcast February 21, 2017

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Analyze and Optimize 32- to 56- Gbps Serial Link Channels Webcast 
Original broadcast January 26, 2017

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Making Accurate Power Integrity Measurements Using an Oscilloscope 
Original broadcast January 12, 2017

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Overcoming 400G Test Challenges using PAM-4 Webcast 
Original broadcast December 13, 2016

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PCI Express®: Techniques for 16 Gbit Deployment Webcast 
Original broadcast September 27, 2016

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PAM-4 Designs – Advanced Characterization and Debug Solutions Webcast 
Original broadcast May 18, 2016

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PCI Express 3.0 Receiver test of ASICs- how to face this challenge - webcast 
When PCIe 3.0 was generated, it was a goal to re-use the existing passive infrastructure - the channels. With nearly double the signal rate (8Gb/s vs. 5Gb/s), the error free transmission now heavily depends on the RX. Therefore it is now normati...

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Practical Approach for Signal Integrity Analysis of High Data Rate Channels Webcast 
Original broadcast July 28, 2016

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DisplayPort 1.3 over Type-C: Taming the Gotchas!  
Original broadcast May 3, 2016

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Identify and Eliminate Crosstalk from Your Designs Using Oscilloscopes Webcast 
Original broadcast April 20, 2016

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USB-PD (Power Delivery) Testing over Type-C Webcast 
Original broadcast March 31, 2016

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Switch Mode Power Supply Measurements and Analysis using Oscilloscopes 
Original broadcast November 18, 2014

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MIPI M-PHY, D-PHY and C-PHY Receiver Testing – Today and Tomorrow 
Original broadcast October 21, 2014

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Jitter Measurements and Real-Time Eye Analysis Using an Oscilloscope Webcast 
Original broadcast May 28, 2015

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Introducing the New Infiniium V-Series High-Performance Oscilloscope Webcast 
Original broadcast April 14, 2015

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Next generation BERT Ensures Signal Integrity in High-speed Digital Designs Webcast 
Original broadcast January 21, 2014

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Ten Oscilloscope Innovations You’ll Want that Didn’t Exist Three Years Ago 
Original broadcast November 12, 2014

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See the New Infiniium S-Series Oscilloscope in this 30 Minute Webcast 
Original broadcast Ocotber 22, 2014

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Do you use Oscilloscopes in the 1 GHz to 6 GHz bandwidth range? 
Original broadcast June 24, 2014

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Network Analysis Back to Basics Webcast 
Recorded broadcast August 21, 2013

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Fixturing and Fixture Removal for Multiport Devices with Non-Standard RF Interfaces Webcast 
Original broadcast March 11, 2014

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Physical Layer design challenges for PCI Express® 3.0 and 2.0 designs 
You will learn advanced techniques for PCI Express phy-layer validation covering the latest PCIe 3.0 specification requirements as well as practical extensions to PCIe 2.0 and 1.1 designs. This seminar analyzes transmitter and receiver performance.

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