Discuter avec un expert

PCIe 2.0/3.0, PCI Express® Design & Test Information Resource Center

Peripheral Component Interconnect Express, officially abbreviated as PCIe® or PCI Express®, is a computer expansion bus standard designed to replace the older bus standards such as PCI. 

PCIe 2.0 doubles the transfer rate of PCIe 1.0 to 5 GT/s and the per-lane throughput rises from 250 MB/s to 500 MB/s.

PCIe 3.0 has a 8 GT/s bit rate which is backward compatible with PCIe 2.0 and effectively delivers double the PCIe 2.0 bandwidth. 

Regardless of the PCIe generation design challenges you are facing, Keysight offers a complete solution set from electrical to protocol. Work with Keysight and achieve your best design.

See Measurement Solution Examples: PCIe 3.0 Transmitter Test    PCIe 3.0 Receiver Test

Explorer les vidéos YouTube 

1-20 sur 20

Sort:
How to Optimize Your SerDes Design During the Pre-layout Phase Webcast 
Live broadcast September 25, 2014; 10am PT / 1pm ET

Webcast

 
Practical Guide to Quickly Making 100G Electrical Measurements Seminar 
Santa Clara, CA - September 17, 2014

Séminaire

 
Keeping up with 10G USB 3.1 Physical Layer Test Challenges Webcast 
Original broadcast January 15, 2014

Webcast - enregistré

 
Discover Keysight’s New AWG: Highest Speed, Bandwidth & Channel Density 
Live broadcast September 10, 2014; 10am PT / 1pm ET

Webcast

 
PCI Express 3.0 Receiver test of ASICs- how to face this challenge - webcast 
When PCIe 3.0 was generated, it was a goal to re-use the existing passive infrastructure - the channels. With nearly double the signal rate (8Gb/s vs. 5Gb/s), the error free transmission now heavily depends on the RX. Therefore it is now normati...

Webcast - enregistré

 
Physical Layer design challenges for PCI Express® 3.0 and 2.0 designs 
You will learn advanced techniques for PCI Express phy-layer validation covering the latest PCIe 3.0 specification requirements as well as practical extensions to PCIe 2.0 and 1.1 designs. This seminar analyzes transmitter and receiver performance.

Webcast - enregistré

 
EMC Back to Basics Webcast 
Original broadcast April 16, 2014

Webcast - enregistré

 
Fixturing and Fixture Removal for Multiport Devices with Non-Standard RF Interfaces Webcast 
Original broadcast March 11, 2014

Webcast - enregistré

 
Simultaneous Switching Noise Analysis in DDR4 applications using Power-Aware IBIS Models Webcast 
Original broadcast May 22, 2014

Webcast - enregistré

 
New Calibration Method Simplifies Measurements of Fixtured Devices Webcast 
Original broadcast July 29, 2014

Webcast - enregistré

 
Fixture De-embedding Techniques for 28 Gb/s Transmitter Measurements Webcast 
Live broadcast January 23, 2014; 10am PT/1pm ET/19:00 CET

Webcast - enregistré

 
Network Analysis Back to Basics Webcast 
Recorded broadcast August 21, 2013

Webcast - enregistré

 
DesignCon 2014 
Jan 28-31, 2014; Santa Clara Convention Center Download papers presented, order the AEF DVD

Salon professionnel

 
Advanced Oscilloscope Measurements – Utilizing Math and Measurements Capability 
Original broadcast June 3, 2014

Webcast - enregistré

 
Simulation-Measurement Workflow for DDR Compliance Webcast 
Original broadcast March 27, 2014

Webcast - enregistré

 
Do you use Oscilloscopes in the 1 GHz to 6 GHz bandwidth range? 
Original broadcast June 24, 2014

Webcast - enregistré

 
Next generation BERT Ensures Signal Integrity in High-speed Digital Designs Webcast 
Original broadcast January 21, 2014

Webcast - enregistré

 
Automate Multilane Gigabit Oscilloscope Testing with Switch Matrix Webcast 
Original broadcast November 20, 2013

Webcast - enregistré

 
Test and Validation of PCIe/NVMe Protocol Designs Webcast 
Original broadcast July 10, 2014

Webcast - enregistré

 
EMI/EMC Analysis for High-Speed Digital Design Webcast 
Live broadcast July 24, 2014; 10am PT/1pm ET/19:00 CET

Webcast