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PCI Express® (PCIe) Design & Test

Peripheral Component Interconnect Express, officially abbreviated as PCIe® or PCI Express®, is a computer expansion bus standard designed to replace the older bus standards such as PCI. 

PCIe 2.0 doubles the transfer rate of PCIe 1.0 to 5 GT/s and the per-lane throughput rises from 250 MB/s to 500 MB/s.

PCIe 3.0 has a 8 GT/s bit rate which is backward compatible with PCIe 2.0 and effectively delivers double the PCIe 2.0 bandwidth. 

PCIe 4.0 at 16 GT/s doubles data rates again, requiring extensive testing and validation to enable speed, while maintaining backward compatibility with earlier generations.

Regardless of the generation of PCIe design you are testing or the PCI Express design challenges you are facing, Keysight offers a complete solution set from design to test. Work with Keysight and gain insights for you best PCIe design.

See measurement solution examples to discover specific solutions for your PCIe needs

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PAM-4 Designs – Advanced Characterization and Debug Solutions Webcast 
Original broadcast May 18, 2016

Webcast - recorded

 
DisplayPort 1.3 over Type-C: Taming the Gotchas!  
Original broadcast May 3, 2016

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Practical Approach for Signal Integrity Analysis of High Data Rate Channels Webcast 
Live broadcast July 28, 2016

Webcast

 
Power Integrity Measurements Webcast – Choosing the Right Tools 
Original broadcast January 6, 2016

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Thunderbolt over Type-C – Overcoming Test Challenges Webcast 
Original broadcast February 24, 2016

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USB 3.1 Receiver Testing including devices using Type-C Webcast 
Original broadcast February 3, 2016

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Mastering Power Integrity Webcast 
Original broadcast January 28, 2016

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Supporting PAM-4 Optical Link Development Webcast 
Original broadcast December 10, 2015

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Digital & Photonics - Webcast Library 
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MIPI M-PHY, D-PHY and C-PHY Receiver Testing – Today and Tomorrow 
Original broadcast October 21, 2014

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Introducing Keysight’s New AWG for Optical and High Speed Digital Test Webcast 
Original broadcast October 8, 2015

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Fundamentals of PCIe® 3.0 EQ Test and Outlook on PCIe 16GT/s RX Test Webcast 
Original broadcast September 30, 2015

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How to Use a SERDES Channel Simulator for PAM-4 Simulations and Analysis Webcast 
Original broadcast July 23, 2015

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MIPI – Overcome Test Challenges to Ensure Interoperability for your PHY Webcast 
Original broadcast June 23, 2015

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Validate PCIe® Power Saving with L1 Substate Analysis Webcast 
Original broadcast June 17, 2015

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Next generation BERT Ensures Signal Integrity in High-speed Digital Designs Webcast 
Original broadcast January 21, 2014

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Optimizing 100G Ethernet Electrical Measurements Webcast 
Original broadcast December 10, 2014

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Ten Oscilloscope Innovations You’ll Want that Didn’t Exist Three Years Ago 
Original broadcast November 12, 2014

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