PCI Express® Design & Test
Peripheral Component Interconnect Express, officially abbreviated as PCIe® or PCI Express®, is a computer expansion bus standard designed to replace the older bus standards such as PCI.
PCIe 2.0 doubles the transfer rate of PCIe 1.0 to 5 GT/s and the per-lane throughput rises from 250 MB/s to 500 MB/s.
PCIe 3.0 has a 8 GT/s bit rate which is backward compatible with PCIe 2.0 and effectively delivers double the PCIe 2.0 bandwidth.
Regardless of the PCIe generation design challenges you are facing, Keysight offers a complete solution set from electrical to protocol. Work with Keysight and gain insights for your best design.
See measurement solution examples to discover specific solutions for your PCIe needs
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Oscilloscopes, Analyzers, Meters
Protocol Analyzers and Exercisers
- U4431A MIPI M-PHY Protocol Analyzer (1)
- HDMI / MHL Protocol Analyzers and Generators (2)
- PCI EXPRESS® Protocol Solutions (4)
- E2960B Series PCIe Test Solutions for PCIe 1.0 and PCIe 2.0 (3)
- N5300 Series Chassis (2)
- Protocol Solutions for USB 3.0/2.0 (2)
- DigRF Protocol Test Products (2)
- SerialTek SAS/SATA BusXpert Analyzers, BusMod Error Injectors, BusGen BIST Generators (2)
- Protocol Analyzers and Exercisers
- Oscilloscopes, Analyzers, Meters
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Jan 28-31, 2014; Santa Clara Convention Center Download papers presented, order the AEF DVD
Electronic Measurement Events in Europe, Middle East & Africa
Electronic Measurement events in Europe, the Middle East, and Africa - seminars, trade shows, user group meetings, webcasts, tutorials and conferences.
Keysight's Events for United Kingdom and Ireland
Welcome to Keysight's Upcoming Events Page for United Kingdom and Ireland
Physical Layer design challenges for PCI Express® 3.0 and 2.0 designs
You will learn advanced techniques for PCI Express phy-layer validation covering the latest PCIe 3.0 specification requirements as well as practical extensions to PCIe 2.0 and 1.1 designs. This seminar analyzes transmitter and receiver performance.
Webcast - recorded
Test and Validation of PCIe/NVMe Protocol Designs Webcast
Original broadcast July 10, 2014
Webcast - recorded