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PCI Express® (PCIe) Design & Test

Peripheral Component Interconnect Express, officially abbreviated as PCIe® or PCI Express®, is a computer expansion bus standard designed to replace the older bus standards such as PCI. 

PCIe 2.0 doubles the transfer rate of PCIe 1.0 to 5 GT/s and the per-lane throughput rises from 250 MB/s to 500 MB/s.

PCIe 3.0 has a 8 GT/s bit rate which is backward compatible with PCIe 2.0 and effectively delivers double the PCIe 2.0 bandwidth. 

Regardless of the generation of PCIe design you are testing or the PCI Express design challenges you are facing, Keysight offers a complete solution set from design to test. Work with Keysight and gain insights for you best PCIe design.

See measurement solution examples to discover specific solutions for your PCIe needs

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DesignCon 2015 
Download Keysight's papers from Technical Conference; Jan 27-29, 2015; Santa Clara Convention Center

Tradeshow

 
Transistor Measurement and Modeling Challenges Seminar 
Various dates and locations

Seminar

 
Debugging Serial Buses In Embedded Designs using Oscilloscopes Webcast 
Original broadcast August 18, 2015

Webcast - recorded

 
How to Use a SERDES Channel Simulator for PAM-4 Simulations and Analysis Webcast 
Original broadcast July 23, 2015

Webcast - recorded

 
PCIe - Assuring Gen4 Tx/Rx Performance with Hot TDR Webcast 
Live broadcast September 9, 2015; 10am PT / 1pm ET

Webcast

 
MIPI – Overcome Test Challenges to Ensure Interoperability for your PHY Webcast 
Original broadcast June 23, 2015

Webcast - recorded

 
Achieving Success at 16 Gigabit Operation with PCI Express® 4.0 Webcast 
Live broadcast September 10, 2015; 10am PT / 1pm ET

Webcast

 
Find Signal Integrity Problems Faster through TDR/TDT Measurements Webcast 
Live broadcast August 27, 2015; 10am PT / 1pm ET

Webcast

 
Validate PCIe® Power Saving with L1 Substate Analysis Webcast 
Original broadcast June 17, 2015

Webcast - recorded

 
Jitter Measurements and Real-Time Eye Analysis Using an Oscilloscope Webcast 
Original broadcast May 28, 2015

Webcast - recorded

 
PAM-4 Transmitter and Receiver Design Characterization Solutions Webcast 
Original broadcast May 21, 2015

Webcast - recorded

 
MIPI Physical Layer Standards and Receiver Test Solutions Webcast 
Original broadcast May 13, 2015

Webcast - recorded

 
DisplayPort 1.3 – PHY Layer Test Requirements Webcast 
Live broadcast May 27, 2015; 10am PT / 1pm ET

Webcast

 
DDR4/LPDDR4 – Overcome the Barriers of Testing and Probing High-Speed Memory Systems Webcast 
Original broadcast April 23, 2015

Webcast - recorded

 
Introducing the New Infiniium V-Series High-Performance Oscilloscope Webcast 
Original broadcast April 14, 2015

Webcast - recorded

 
Advanced Triggering and Signal Isolation using InfiniiVision X-Series Oscilloscopes Webcast 
Original broadcast April 7, 2015

Webcast - recorded

 
10G USB 3.1 – Keeping Up with the Physical Layer Test Challenges Webcast 
Original broadcast March 25, 2015

Webcast - recorded

 
USB 3.1 - Gen2 10Gbps Receiver Test Challenges Webcast 
Original broadcast March 11, 2015

Webcast - recorded

 
PAM-4 Solutions for Transmit and Receive Design Characterization Webcast 
Original broadcast October 23, 2014

Webcast - recorded

 
Power Integrity Measurements Webcast – Choosing the Right Tools 
Original broadcast February 26, 2015

Webcast - recorded

 
PCB Materials, Simulations, and Measurements for 32 Gb/s Webcast 
Original broadcast January 22, 2015

Webcast - recorded

 
Next generation BERT Ensures Signal Integrity in High-speed Digital Designs Webcast 
Original broadcast January 21, 2014

Webcast - recorded

 
Webcast: RF Measurements You Didn't Know Your Oscilloscope Could Make 
Original broadcast , January 21, 2015

Webcast - recorded

 
Optimizing 100G Ethernet Electrical Measurements Webcast 
Original broadcast December 10, 2014

Webcast - recorded

 
Overcoming Test Challenges of 100Gb Ethernet and Beyond Webcast 
Live broadcast January 15, 2015; 10am PT / 1pm ET

Webcast

 

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