Contact an Expert

PCIe 2.0/3.0, PCI Express® Design & Test Information Resource Center

Peripheral Component Interconnect Express, officially abbreviated as PCIe® or PCI Express®, is a computer expansion bus standard designed to replace the older bus standards such as PCI. 

PCIe 2.0 doubles the transfer rate of PCIe 1.0 to 5 GT/s and the per-lane throughput rises from 250 MB/s to 500 MB/s.

PCIe 3.0 has a 8 GT/s bit rate which is backward compatible with PCIe 2.0 and effectively delivers double the PCIe 2.0 bandwidth. 

Regardless of the PCIe generation design challenges you are facing, Keysight offers a complete solution set from electrical to protocol. Work with Keysight and achieve your best design.

See Measurement Solution Examples: PCIe 3.0 Transmitter Test    PCIe 3.0 Receiver Test

1-11 of 11

Sort:
10 Oscilloscope Innovations You’ll Want that Didn’t Exist 3 Years Ago 
Live broadcast November 12, 2014; 10am PT / 1pm ET

Webcast

 
Automate Multilane Gigabit Oscilloscope Testing with Switch Matrix Webcast 
Original broadcast November 20, 2013

Webcast - recorded

 
DesignCon 2014 
Jan 28-31, 2014; Santa Clara Convention Center Download papers presented, order the AEF DVD

Tradeshow

 
Discover Keysight’s New AWG: Highest Speed, Bandwidth & Channel Density 
Original broadcast September 10, 2014

Webcast - recorded

 
Fixture De-embedding Techniques for 28 Gb/s Transmitter Measurements Webcast 
Live broadcast January 23, 2014; 10am PT/1pm ET/19:00 CET

Webcast - recorded

 
Keeping up with 10G USB 3.1 Physical Layer Test Challenges Webcast 
Original broadcast January 15, 2014

Webcast - recorded

 
MIPI M-PHY, D-PHY and C-PHY Receiver Testing – Today and Tomorrow 
Original broadcast October 21, 2014

Webcast - recorded

 
Next generation BERT Ensures Signal Integrity in High-speed Digital Designs Webcast 
Original broadcast January 21, 2014

Webcast - recorded

 
PAM-4 Solutions for Transmit and Receive Design Characterization 
Live broadcast October 23, 2014; 10am PT / 1pm ET

Webcast

 
PCI Express 3.0 Receiver test of ASICs- how to face this challenge - webcast 
When PCIe 3.0 was generated, it was a goal to re-use the existing passive infrastructure - the channels. With nearly double the signal rate (8Gb/s vs. 5Gb/s), the error free transmission now heavily depends on the RX. Therefore it is now normati...

Webcast - recorded

 
Surmounting the Challenges of 16 Gigabit Operation with PCI Express Webcast 
Original broadcast Ocotber 1, 2014

Webcast - recorded