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DDR, DDR2, DDR3, DDR4 Memory Design & Test

Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) is implemented in several forms today:

Keysight’s solutions for DDR memory applications are driven and supported by Keysight experts that are active in the Joint Electronic Devices Engineering Council (JEDEC). Our involvement in standards groups and their related workshops, and specification development enables Keysight to bring the right solutions to the market when our customers need them.

Regardless of the DDR generation design challenges you are facing, Keysight offers a complete solution set from electrical to protocol. Work with Keysight and gain insights for your best design.

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10G SuperSpeed USB 3.1 Physical Layer Test Challenges and Solutions Seminar 
April 22, 2015; Santa Clara, CA

Seminar

 
10G USB 3.1 – Keeping Up with the Physical Layer Test Challenges Webcast 
Original broadcast March 25, 2015

Webcast - recorded

 
Accelerate DDR4/LPDDR3 Memory Debug with Bus level Signal Integrity Insight Webcast 
Original broadcast March 4, 2014

Webcast - recorded

 
Accelerate FPGA Debug by Applying Latest Tools and Methods Webcast 
Original broadcast June 10, 2014

Webcast - recorded

 
Best practices in implementing boundary scan on limited access boards 
Original broadcast December 18, 2014

Webcast - recorded

 
Boundary Scan Webcast Series 
Live and on-demand webcasts

Webcast

 
Common DFT guidelines for implementing boundary scan on limited access boards webcast 
Original broadcast September 11, 2014

Webcast - recorded

 
DDR4/LPDDR4 – Overcome the Barriers of Testing and Probing High-Speed Memory Systems Webcast 
Live broadcast April 23, 2015; 10am PT / 1pm ET

Webcast

 
DesignCon 2014 
Jan 28-31, 2014; Santa Clara Convention Center Download papers presented, order the AEF DVD

Tradeshow

 
DesignCon 2015 
Download Keysight's papers from Technical Conference; Jan 27-29, 2014; Santa Clara Convention Center

Tradeshow

 
DesignCon 2015 - Keysight Papers  
Download the Keysight presentations at the DesignCon 2015 Technical Conference

Tradeshow

 
Embedded testing of Intel Haswell and Broadwell chipsets on limited access client boards webcast 
Original broadcast November 13, 2014

Webcast - recorded

 
EMI/EMC Analysis for High-Speed Digital Design Webcast 
Live broadcast July 24, 2014; 10am PT/1pm ET/19:00 CET

Webcast

 
Extending boundary scan tests to improve test coverage of limited access boards webcast 
Original broadcast September 25, 2014

Webcast - recorded

 
Extraction, Verification, and Usage of a Short Haul Opto VCSEL Model Webcast 
Live broadcast May 28, 2015; 10am PT / 1pm ET

Webcast

 
Fixturing and Fixture Removal for Multiport Devices with Non-Standard RF Interfaces Webcast 
Original broadcast March 11, 2014

Webcast - recorded

 
High-Speed Digital Design and Test Strategies Canadian Seminar Tour 
Various dates and locations in Canada

Seminar

 
How to Achieve Compliance to the New 1E-16 BER Contour Spec in DDR4 
Original broadcast November 6, 2014

Webcast - recorded

 
How to Optimize Your SerDes Design During the Pre-layout Phase Webcast 
Original broadcast September 25, 2014

Webcast - recorded

 
Insight Seminar Series - Advanced Measurements Lab 
Various dates and locations in 2015

Seminar

 
Introducing the New Infiniium V-Series High-Performance Oscilloscope Webcast 
Original broadcast April 14, 2015

Webcast - recorded

 
Introduction to the Keysight x1149 Boundary Scan Analyzer Webcast 
Original broadcast August 26, 2014; 9am PT / 12pm ET

Webcast - recorded

 
IPC Tech Summit 
Raleigh, NC; October 28 - 30, 2014

Tradeshow

 
Jitter Measurements and Real-Time Eye Analysis Using an Oscilloscope Webcast 
Live broadcast May 28, 2015; 10am PT / 1pm ET

Webcast

 
Maximizing test coverage of multiple limited access boards by linking multiple boundary scan chains 
Original broadcast October 9, 2014

Webcast - recorded

 

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