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RFIC and MMIC Foundry Partners 
Brief overview of Keysight EEsof EDA RFIC and MMIC Foundry Partners resources.

FAQ 2014-08-14

 
Device Modeling Insights From The Keysight Experts 
Keysight Technologies highlights its experts in the field of device modeling and chacterization.

FAQ 2013-02-04

 
What is SCANSTA112 device? 
The SCANSTA112 device is a 7-port multidrop IEEE 1149.1 (JTAG) multiplexer design to connect boundary scan chains into a single chain as well as the ability to remove a board from the system and retain test access to the remaining chains.

FAQ 2012-12-01

 
What are the failures that boundary scan test can detect? 
Boundary Scan test will be able to diagnose the following failures:

FAQ 2012-12-01

 
What is the CAPTURE State?  
During the CAPTURE state, data or instruction bits are loaded in parallel into data or instruction registers. The CAPTURE-DR (Data Register) loads data bits into the specified data register. CAPTURE-IR (Instruction Register) loads instruction bits into the Instruction Register.

FAQ 2012-10-01

 
Why do I need to hold the state of certain pins/nodes? 
Non-boundary scan devices such as DDR or flash memories need to hold one or more nodes (chip select/enable) to fixed states during boundary scan testing, so that the device is disabled during boundary scan testing and its output pins (i.e. data) are not activated, as otherwise, it will cause unstable tests or damage to the circuitry. Boundary scan “hold states” are node/device pins on a board that are held to a logic of 1 or 0 by a boundary scan driver on the node, when the boundary scan device driver/output pin is in EXTEST.

FAQ 2012-10-01

 
What is the Boundary Scan device Test Operation mode? 
During the boundary scan device test operation mode, a single boundary register cell routes input and output signals so the device's core logic essentially ignores the inputs and outputs.

FAQ 2012-09-01

 
What is the Boundary Scan device Normal Operation mode? 
When the device is operating under the normal mode, the boundary register is transparent. Signals can pass through the boundary scan cells freely and the device operates as it would without test cells. In this mode, test data is captured in the boundary register cells, then shifted through the boundary register out to TDO.

FAQ 2012-09-01

 
我的 FieldFox 分析仪为什么启动不了? 
开机问题最常见的原因是电池电量已经放光。

FAQ 2012-08-15

 
What is Run-Test/Idle State?  
The run-test/idle state is a TAP controller state where once entered, the controller state will remain as long as the test mode state (TMS) is held low.

FAQ 2012-08-01

 
What is Test-Logic-Reset State?  
At the test-logic-reset controller state, the test logic is disabled so that normal operation of the boundary scan device can proceed unhindered.

FAQ 2012-08-01

 
What is STAPL? 
STAPL stands for Standard Test and Programming Language to support programming of programmable logic devices (PLD).

FAQ 2012-07-01

 
What is a bus wire test?  
The bus wire test looks only for opens on all the bussed boundary scan devices that are not tested by the interconnect test.

FAQ 2012-07-01

 
在电池充电器停止充电之前,最大直流输入电压是多少? 
21-22 V。

FAQ 2012-06-01

 
如何重新校准 FieldFox 电池组? 
使用 N9910X-872 重新校准电池组。

FAQ 2012-06-01

 
What is IEEE Standard 1149.7? 
IEEE Standard (Std) 1149.7 is a standard for reduced-pin and enhanced-functionality test access port (TAP) and boundary scan architecture.

FAQ 2012-06-01

 
What is IEEE Standard 1581? 
The IEEE Standard (Std) 1581 is the standard for Static Component Interconnection Test Protocol and Architecture. The IEEE Std 1581 targets testing for low-cost, complex DDR memory devices, which would be able to communicate through another semiconductor device with an IEEE Std 1149.1 boundary scan capability.

FAQ 2012-06-01

 
如何识别 FieldFox 的电路板版本? 
参见指导

FAQ 2012-06-01

 
What are the IEEE standards that are supported or which are being proposed for support by Cover-Extend Technology? 
The available IEEE standards/drafts concerning Cover-Extend Technology are IEEE 1149.1 - IEEE Standard Test Access Ports and Boundary Scan Architecture.

FAQ 2012-05-01

 
What is Cover-Extend Technology? 
Cover-Extend Technology (CET) is a hybrid between VTEP and boundary scan. It draws the best from what each technology offers and enhances the overall capability of Keysight in-circuit test systems.

FAQ 2012-05-01

 
What TAP signals are sampled during the rising edge of a TCK signal? 
The test mode state (TMS) and test data in (TDI) signals are sampled into the test logic on the rising edge of a test clock (TCK) signal.

FAQ 2012-04-01

 
What TAP signals are sampled during the falling edge of a TCK signal? 
The test data out (TDO) signals of the test access port (TAP) are sampled into the test logic on the falling edge of a test clock (TCK) signal.

FAQ 2012-04-01

 
How do I determine the maximum test clock (TCK) frequency of the boundary scan device? 
The boundary scan device test clock (TCK) information is described in the boundary scan description language (BSDL) at the TAP port identification which assigns a special meaning to these signals.

FAQ 2012-03-01

 
What is a Compliance Enable pin? 
Compliance enable pins are device pins that must be held at a static logic state (0 or 1) before the device enters into any 1149.1 activities.

FAQ 2012-03-01

 
What is a Bypass Instruction? 
The Bypass Instruction is an IEEE 1149.1 mandatory instruction which select the single bit Bypass register between the TDI and TDO.

FAQ 2012-02-01

 

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