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Digital Design & Interconnect Standards

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In digital standards, every generational change puts new risks in your path. We see it first hand when creating our products and working with engineers like you. Keysight’s solution set for high-speed digital test is a combination of instrumentation and broad expertise built on our ongoing involvement with industry experts. By sharing our latest experiences, we can help anticipate challenges and accelerate your ability to create products you’ll be proud of.

Keysight - Insights for your best design

Achieve signal integrity in high-speed design with these useful tools, demos, videos and more . Learn more about Digital Design & Interconnect solutions from Keysight. 
 

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ADS in 3D: Speed Your Design with Integrated 3D EM Simulation 
Originally broadcast March 24, 2010

Webcast - recorded

 
Astonishing Enhancements to Signal Integrity EDA Tools Using Video Game 3D Glasses and GPUs 
Original broadcast Jan 21, 2010

Webcast - recorded

 
Case Study: Overcoming Return-path Discontinuity in DDR3/GDDR5 Memory Controller Packages 
Original broadcast October 13, 2011

Webcast - recorded

 
Fixture De-embedding Techniques for 28 Gb/s Transmitter Measurements Webcast 
Live broadcast January 23, 2014; 10am PT/1pm ET/19:00 CET

Webcast - recorded

 
Genesys Webcasts - "How-To-Design" series  
Originally broadcast in 2009. Access the 6 WebEX recordings

Webcast - recorded

 
How to Achieve Compliance to the New 1E-16 BER Contour Spec in DDR4 
Original broadcast November 6, 2014

Webcast - recorded

 
How to Optimize Your SerDes Design During the Pre-layout Phase Webcast 
Original broadcast September 25, 2014

Webcast - recorded

 
Innovations in EDA: Multi-Technology RF Design Using the New Advances in ADS 2011 
Originally broadcast March 1, 2011

Webcast - recorded

 
Innovations in EDA: Opto-Electronic Signal Integrity on Optical Fiber Chip-to-Chip Link 
Originally broadcast April 7, 2011

Webcast - recorded

 
Innovations in EM Simulation for High Speed Digital Design 
Original broadcast Nov 18, 2010; Part of the Series: Signal Integrity for High Speed Digital Interconnects.

Webcast - recorded

 
Overcome High Speed Digital Design Challenges Webcast Series 
Series of live and on-demand webcasts

Webcast - recorded

 
Signal Integrity: Include Post-layout PCB Artwork into your Eye Diagram and BER Contour Simulation 
Originally broadcast May 5, 2010. Part of the Series: Signal Integrity for High Speed Digital Interconnects.

Webcast - recorded

 
Simulation-Measurement Workflow for DDR Compliance Webcast 
Original broadcast March 27, 2014

Webcast - recorded

 
Simultaneous Switching Noise Analysis in DDR4 applications using Power-Aware IBIS Models Webcast 
Original broadcast May 22, 2014

Webcast - recorded

 
Using IBIS AMI Models as ‘Executable Data sheets’ in High Speed Digital Interconnect Simulations 
Originally broadcast Sept 9, 2010. Part of the Series: Signal Integrity for High Speed Digital Interconnects.

Webcast - recorded

 
Which EM Solver Should I Use? 
Originally broadcast June 15, 2010

Webcast - recorded