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Digital Design & Interconnect Standards

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In digital standards, every generational change puts new risks in your path. We see it first hand when creating our products and working with engineers like you. Keysight’s solution set for high-speed digital test is a combination of instrumentation and broad expertise built on our ongoing involvement with industry experts. By sharing our latest experiences, we can help anticipate challenges and accelerate your ability to create products you’ll be proud of.

Keysight - Insights for your best design

Achieve signal integrity in high-speed design with these useful tools, demos, videos and more . Learn more about Digital Design & Interconnect solutions from Keysight. 
 

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New Calibration Method Simplifies Measurements of Fixtured Devices Webcast 
Original broadcast July 29, 2014

Webcast - recorded

 
Simulation-Measurement Workflow for DDR Compliance Webcast 
Original broadcast March 27, 2014

Webcast - recorded

 
ADS in 3D: Speed Your Design with Integrated 3D EM Simulation 
Originally broadcast March 24, 2010

Webcast - recorded

 
Genesys Webcasts - "How-To-Design" series  
Originally broadcast in 2009. Access the 6 WebEX recordings

Webcast - recorded

 
Which EM Solver Should I Use? 
Originally broadcast June 15, 2010

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Primer: A Day in the Life of your Cell Phone 
Original broadcast July 24, 2014

Webcast - recorded

 
Overcome High Speed Digital Design Challenges Webcast Series 
Series of live and on-demand webcasts

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Case Study: Overcoming Return-path Discontinuity in DDR3/GDDR5 Memory Controller Packages 
Original broadcast October 13, 2011

Webcast - recorded

 
Automate Multilane Gigabit Oscilloscope Testing with Switch Matrix Webcast 
Original broadcast November 20, 2013

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Signal Integrity: Include Post-layout PCB Artwork into your Eye Diagram and BER Contour Simulation 
Originally broadcast May 5, 2010. Part of the Series: Signal Integrity for High Speed Digital Interconnects.

Webcast - recorded

 
Simultaneous Switching Noise Analysis in DDR4 applications using Power-Aware IBIS Models Webcast 
Original broadcast May 22, 2014

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Using Logic Analysis to Find Root Cause of Digital Design Errors Webcast 
Recorded broadcast December 17, 2013

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Fixture De-embedding Techniques for 28 Gb/s Transmitter Measurements Webcast 
Live broadcast January 23, 2014; 10am PT/1pm ET/19:00 CET

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Innovations in EM Simulation for High Speed Digital Design 
Original broadcast Nov 18, 2010; Part of the Series: Signal Integrity for High Speed Digital Interconnects.

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Accelerate FPGA Debug by Applying Latest Tools and Methods Webcast 
Original broadcast June 10, 2014

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Astonishing Enhancements to Signal Integrity EDA Tools Using Video Game 3D Glasses and GPUs 
Original broadcast Jan 21, 2010

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Innovations in EDA: Multi-Technology RF Design Using the New Advances in ADS 2011 
Originally broadcast March 1, 2011

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EMC Back to Basics Webcast 
Original broadcast April 16, 2014

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Innovations in EDA: Opto-Electronic Signal Integrity on Optical Fiber Chip-to-Chip Link 
Originally broadcast April 7, 2011

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Using IBIS AMI Models as ‘Executable Data sheets’ in High Speed Digital Interconnect Simulations 
Originally broadcast Sept 9, 2010. Part of the Series: Signal Integrity for High Speed Digital Interconnects.

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DDR memory Characterization Using a Mixed Signal Oscilloscope Webcast 
Original broadcast October 16, 2013

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Network Analysis Back to Basics Webcast 
Recorded broadcast August 21, 2013

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Physical Layer design challenges for PCI Express® 3.0 and 2.0 designs 
You will learn advanced techniques for PCI Express phy-layer validation covering the latest PCIe 3.0 specification requirements as well as practical extensions to PCIe 2.0 and 1.1 designs. This seminar analyzes transmitter and receiver performance.

Webcast - recorded

 
MIPI Physical Layer Transmitter Test Solutions Webcast 
Original broadcast April 2, 2014

Webcast - recorded