Here’s the page we think you wanted. See search results instead:

 

Contact an Expert

Digital Design & Interconnect Standards

In digital standards, every generational change puts new risks in your path. We see it first hand when creating our products and working with engineers like you. Keysight’s solution set for high-speed digital test is a combination of instrumentation and broad expertise built on our ongoing involvement with industry experts. By sharing our latest experiences, we can help anticipate challenges and accelerate your ability to create products you’ll be proud of.

Keysight - Insights for your best design

Learn more about Digital Design & Interconnect solutions from Keysight. 

Keysight RF and Digital Learning Center - A commitment to learning with industry experts 
 

Explore YouTube Videos 

Refine the List

remove all refinements

By Industry/Technology

By Type of Content

By Product Category

76-100 of 148

Sort:
Accurate Calibration of Receiver Stress Test Signals for PCI Express® Rev. 3.0 - Application Note 
This paper describes the calibration of the receiver-stress signal according to the base specification of PCIe3. The calibration of the RX test signal is different from PCIe 2.0.

Application Note 2011-06-22

A Simple, Powerful Method to Characterize Differential Interconnects 
The Automatic Fixture Removal (AFR) process is a new technique to extract accurate, high bandwidth models of interconnects that is both simple and accurate.

Application Note 2011-06-17

PDF PDF 3.48 MB
Keysight Method of Implementation (MOI) for SATA SI Compliance Test 
Keysight Method of Implementation (MOI) for SATA SI Compliance Test Using Keysight E5071C ENA Network Analyzer Option TDR

Application Note 2011-01-12

PDF PDF 1.41 MB
Keysight Method of Implementation (MOI) for SATA RXTX Impedance Compliance Test 
Keysight Method of Implementation (MOI) for SATA RXTX Impedance Compliance Test Using Keysight E5071C ENA Network Analyzer Option TDR

Application Note 2011-01-12

PDF PDF 1.19 MB
Understanding the Kramers-Kronig Relation Using A Pictorial Proof 
The Kramers-Kronig relation lets us build a causal time-domain model from bandlimited s-parameters. This pictorial proof aids understanding of the physics of causality and hence the validity of this approach.

Application Note 2010-03-31

Keysight HDMI 1.4 Whole Solution 
Media Recommended in CTS 1.4

Application Note 2009-11-20

PDF PDF 1.89 MB
Using ADS for Signal Integrity Optimization 
This white paper shows how to replace a multi-dimensional sweep of a long running PRBS time-domain simulation (including manual data evaluation) by short, channel-pulse characterization in the Advanced Design System to efficiently optimize a channel.

Application Note 2009-10-19

Testing of RF ICs with DigRF Interconnects - Application Note 
Testing of RF ICs with DigRF Interconnects

Application Note 2009-09-11

Keysight MOI for SATA TXRX Tests Using Keysight 86100C TDR 

Application Note 2009-09-10

PDF PDF 479 KB
Using the Keysight Infiniium Series Real-time Oscilloscope to Validate the DigRF 
The DigRF v3 standard presents new digital hardware validation challenges for mobile wireless development as the links between the baseband (BB) ICs and the radio frequency (RF) ICs transition from an analog interface to a digital interface.

Application Note 2009-05-27

Improving the Accuracy of Optical Transceiver Extinction Ratio Measurements (AN 1550-9) 
This paper discusses extinction ratio - measurement challenges and causes of measurement uncertainty & variability. In addition, it describes methods for reducing uncertainties caused by non-ideal performance of standard reference receivers.

Application Note 2009-02-21

Find and identify the causes of data corruption and elusive failures 
The Protocol-decode software allows you to track and fix infrequent glitches and other signal anomalies that might otherwise be difficult to find.

Application Note 2008-12-19

PDF PDF 360 KB
DDR Probing for Physical Layer and Functional Testing 
Probing is the key to accessing signals and validating your designs. Although you may normally probe at signal vias or designed-in probe points, for DDR these do not always provide good signal integrity.

Application Note 2008-12-19

PDF PDF 617 KB
Ensuring Compliance and Interoperability of DDR Designs 
The Joint Electronic Devices Engineering Council (JEDEC) specification requires a large number of test parameters to be verified for DDR compliance – a time-consuming exercise if you make the measurements manually.

Application Note 2008-12-19

PDF PDF 379 KB
Debugging Signal Integrity and Protocol Layers on DDR Designs 
As DDR data transmission rates increase, signal integrity and clarity become critical concerns. So one of the primary challenges with DDR is debugging failures.

Application Note 2008-12-19

PDF PDF 984 KB
PCI Express® Revision 2 - Receiver Testing With J-BERT N4903A and 81150A Pulse - Application Note 
Receiver Testing With J-BERT N4903A and 81150A Pulse

Application Note 2008-12-03

PDF PDF 1000 KB
Boosting PLL Design Efficiency From free-running VCO characterizations to closed-loop PLL evaluation 
This application note describes introduces practical solutions for VCO/PLL performance evaluation and gives actual examples of parameter measurements using the E5052B.

Application Note 2008-11-21

Characterizing Clock Jitter through Phase Noise Measurements Speeds up Design Verification Process 
This white paper discusses a new measurement method for obtaining highly accurate low random jitter (RJ) measurements and performing real-time analysis of RJ and periodic jitter (PJ) of components.

Application Note 2008-11-20

Upgrade to PCI Express 2.0© Receiver Test - Application Note 
The 15431A is a filter set for the 81150A. It generates the random jitter profile for testing PCI Express 2.0 receivers, to be used in conjunction with the N4903A. This fact sheet explains the upgrade.

Application Note 2008-10-24

PDF PDF 348 KB
Benefits of using PCI Express 2.0. - Application Note 
An overview of the main features and benefits of using PCI Express 2.0

Application Note 2008-10-17

PDF PDF 764 KB
A Time-Saving Method for Analyzing Signal Integrity in DDR Memory Buses 
This application note covers new tools and measurement techniques for characterizing and validating signal integrity of DDR (double data rate synchronous dynamic random access memory) signals.

Application Note 2008-09-10

Method of Implementation (MOI) for DisplayPort Sink Compliance Test - Application Note 
Method of Implementation (MOI) for DisplayPort Sink Compliance Test

Application Note 2008-08-18

PDF PDF 1.87 MB
Solutions for MB-OFDM Ultra-Wideband (UWB) Application Note 
Application note describes hardware and software for ultra wideband (UWB) testing.

Application Note 2008-08-10

Calibrating optical stress signals for characterizing 10 Gb/s optical transceivers - App Note 
Calibrating optical stress signals for characterizing 10 Gb/s optical transceivers

Application Note 2008-06-10

10 Hints for Getting the Most from your Frequency Counter 
Maximize the results you get from your frequency counter through 10 hints from better from understanding the architecture to making faster measurements.

Application Note 2008-04-18

Previous 1 2 3 4 5 6 Next