N4903A High-Performance Serial BERT with complete jitter tolerance testing
|Product Status:||Discontinued | Currently Supported|
A replacement for this product is available:
Key Features & Specifications
- 150 Mb/s to 7 Gb/s or to 12.5 Gb/s pattern generator and error detector
- >0.5 UI calibrated and integrated jitter injection.
- Excellent signal performance and sensitivity
- Built-in clock data recovery with tunable and compliant loop bandwidth
Available Configurations for N4903A
NEW - J-BERT N4903B High-performance Serial BERT
The last order date for the A-version of the J-BERT N4903A high-performance serial BERT will be April 30, 2010. The recommended replacement product is the J-BERT N4903B, which offers more jitter injection capabilities, half-rate clocking support, built-in CDR and cleaner output performance at a comparable price. N4903A software and hardware upgrade options can be ordered until April 30, 2011. Upgrades from the N4903A to the B version are possible by ordering N4903B-UAB. J-BERT N4903B.
J-BERT N4903B High-performance Serial BERT The only complete jitter tolerance test – now for next generation of forwarded and embedded clock designs such as QPI, PCIe, DisplayPort, SATA, USB, FB-DIMM, Fibre Channel, 10GbE.
The Keysight J-BERT N4903A High-Performance Serial BERT provides the only complete jitter tolerance test solution for characterization of serial gigabit devices.
The J-BERT offers complete, integrated and calibrated jitter composition for stressed eye testing of receivers up to 12.5 Gb/s.
Automated and compliant jitter tolerance testing allows quick and accurate characterization for all popular serial bus standards, such as PCIeTM, SATA, FB-DIMM, Fibre Channel, CEI, Gigabit Ethernet and XFP/XFI.
The J-BERT matches to latest serial bus interfaces perfectly with its ability to analyze undeterministic traffic, generate complex pattern sequences, subrate clock outputs. Clockless and differential interfaces can be tested.
The J-BERT is an expandable, future-proof BERT platform where all options can be configured to the current test needs and upgraded later when those needs change.
It is the ideal choice for R&D and validation teams who characterize and stress chips and transceiver modules with serial I/O ports up to 12.5 Gb/s.
|Clean Eye||Eye Diagram/Contour/Mask|
|Stressed Eye||Automated Jitter Tolerance|
|Fastest Total Jitter||Jitter Composition|
Have a look at the Animated J-BERT Overview
- Operating range 150 Mb/s to 7 Gb/s or to 12.5 Gb/s provides enough margin for today’s and tomorrows serial interfaces
- >0.5 UI jitter injection. Calibrated and integrated jitter injection (opt. J10, J20). All in one box: PJ, SJ, RJ, BUJ, ISI and sinusoidal interference for stressed eye test of a receiver
- Cleanest eyes with transition times <20 ps and <9 ps pp jitter for accurate measurements
- Pattern generator options for 7Gb/s and 12.5Gb/s
- Best match for serial interfaces: Built-in CDR, differential I/Os
- Clock data recovery (CDR) operates at 1Gb/s to 12.5 Gb/s and tunable loop bandwidth (option CTR) for compliant measurements
- Subrate clocks with any ratio 1:n
- Bit recovery mode (opt. A01) to analyze undeterministic traffic
- Pattern sequencer and capture to simplify handling of complex data patterns
- External Delay Control Input for injection of any external jitter
- Automated jitter tolerance characterization and compliance tests
- SSC - Spread Spectrum Clocking (opt. J11)
- Jitter tolerance compliance (opt. J12) testing : PCIeTM, SATA, Fibre Channel, FB-DIMM, CEI, 10 GbE, XFP/XFI
- Fast Total Jitter measurement
- All options upgradeable
J-BERT awards: J-BERT's technology leadership has been honored by our customers and key technical publications with several product awards. Read more
PCIe is a trademark of the PCI-SIG
Training & Events