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Key Features & Specifications

Automated stress calibration with test software N5990A-101

  • PCI Express 1.0a, 2.5 GT/s
  • PCI Express 1.1, 2.5 GT/s
  • PCI Express 2.0, 5.0 GT/s and 2.5 GT/s
  • PCI Express 3.0, 8.0 GT/s, 5.0 GT/s and 2.5 GT/s
  • PCI Express 4.0, 16 GT/s (beta version)
  • Supports PCI Express Base Specification as well as CEM form factor compliance testing and U.2 form factor compliance testing (8 GT/s only)
  • PCIe Compliance tests, including 2.8 and 2.9, as well as characterization measurements like transmit equalization coefficient matrix scan, jitter tolerance search and sensitivity tests
  • Optional link equalization test 2.3, 2.4, 2.7, 2.10 and 2.11, requires option N5990A-501

Highly integrated J-BERT M8020A for a complete test solution

  • Data rate options of 8 GT/s and 16 GTs. Select M8041A-C16 for PCI Express data rates up to 16 GT/s. Select M8041A-C08 for coverage up to 8 GT/s.
  • Built-in pre- and post-cursor de-emphasis, option M8041A-0G4
  • All sinusoidal interference and jitter sources built-in, options M8041A-0G7 and M8041A-0G3
  • Built-in adjustable intersymbol interference for J-BERT M8020A’s output, option M8041A-0G5
  • Built-in Multiplying PLL for 100MHz reference clock with SSC (mother board test), option M8041A-0G6
  • Interactive link training for PCIe 8 GT/s and 16 GT/s, option M8041A-0S4 (8 GT/s and 16 GT/s) or option M8041A-0S1 (8 GT/s only)
  • Loopback mode error counter while SKP Ordered Set length varies, option M8041A-0S2

Description

Keysight offers a complete and accurate receiver (RX) test solution based on the J-BERT M8020A high-performance BERT, an Infiniium 90000 Series high-performance oscilloscope with at least 25 GHz bandwidth and the N5990A test automation software. To increase test efficiency switch matrixes for RX as well TX testing and remote programmable power strips are supported optionally. Keysight supports receiver and link equalization testing of ASICs (according to the base specification), CEM add-in cards and CEM motherboards as well as U.2 devices and hosts (according to the PCI Express Architecture PHY Test Specification).

See Recommended Configuration for Keysight PCI Express Receiver Test Setup.

Accurate PCI Express Receiver Characterization

With the new release of PCI Express 3.0, PCI SIG now requires receiver testing for PCI Express compliance. Transmission rates of 8 GT/s and 16 GT/s cause significant design and test challenges for ASICs, chips, and boards.
Keysight offers a complete test solution for accurate characterization of PCI Express receiver ports during R&D and validation test. The test solution covers PCI Express standards 1.0a, 1.1, 2.0, 3.0 and 4.0 (beta) and all PCIe transfer rates including 16 GT/s are supported. Next to ASIC testing (according to the PCI Express Base Specification) the test setup can be configured for CEM form factor and U.2 form factor testing (PCI Express 3.0 8 GT/s only).

Key Challenges of PCI Express 3.0 and 4.0 Receiver Testing

Transmitting 8 GT/s over traditional PC board traces causes significant signal degradations. Testing the receiver ensures it can detect bits properly (at a BER level of 10-12) even at worst-case stress conditions. For PCI Express 3.0 receiver test uses an eye diagram to analyze variations of voltage and jitter as defined by the base PCIe specification. Test challenges include optimizing transmit and receive equalization with 3 taps, emulating three different lengths of calibration channels, device link training with 128/130 bit coded pattern sequences, as well as specific periodic and random jitter conditions. Even more challenging is the implementation of the newly required calibration procedure for PCI Express 3.0 & 4.0 compliant stress conditions as a receiver would see them after applied equalization. This procedure requires post-processing of signals captured at an accessible test point.
The stress signal for 16 GT/s is adjusted by varying ISI, SJ and DM-SI rather than varying launch amplitude, RJ and DM-SI for the 8 GT/s stress signal. Another important change is that a mated CEM connector is now required to be part of the base specification test channel for 16 GT/s receiver testing. While this mated CEM connector has to reside on channel boards, the adjustable ISI element can be implemented either by a selection of ISI traces of different length or more conveniently by using the adjustable ISI option of the J-BERT M8020A data output stages.
The stressed voltage and stressed jitter tests are combined into just one receiver test at 16 GT/s.

PCI Express 4.0 Base Specification Receiver Test Set J-BERT

PCI Express 4.0 Base Specification Receiver Test Setup

 

Key Challenges of PCI Express Link Equalization Testing

The most significant change from PCIe 2.0 to 3.0 other than the bit rate increase is the requirement for dynamic link equalization. Link equalization is critical for PCIe 3.0 because of the increase rate and no change in specification for the transmission path causing increased signal integrity challenges. Signal equalizers are used at one or more locations in the link to compensate for signal anomalies by boosting the high-frequency components. Link equalization testing verifies the optimization of the link between a transmitter and receiver. The test solution acts as a link partner, and quickly negotiates transmitter to receiver communications using protocol handshakes.

Receiver link equalization testing adds stress signals to the standard receiver tests. A loopback process is used to train the link, as different pre-shoot and de-emphasis parameters are applied to fine tune the link’s performance. The link is successfully trained once the receiver achieves the required bit error rate.
Transmitter equalization testing verifies that the device under test works correctly for transmitter tests 2.3, 2.4 and 2.7, in a specified time as specified in tests 2.4 and 2.7. The BERT transmits using equalization to train the device under test during the loopback stage. The device under test's signal is analyzed using an eye diagram generated by an oscilloscope. Response times of a device under test are verified by capturing the handshake between the BERT and the device under test.

PCI Express 3.0 Link Equalization Test 2.4 J-BERT M8020A

PCI Express Transmitter Link Equalization Test of an Add In Card

 

PCI Express RX Test J-BERT M8020A optional switch matrix

PCI Express RX Test Station Configuration

 

PCI Express RX and Link EQ Test Report J-BERT M8020A

Results can be reported as Excel workbook or as HTML report. Optionally results can be collected in a database.
 

Recommended Instrument Configuration for Keysight PCI Express Receiver Test Setup

Keysight RF and Digital Learning Center - A commitment to learning with industry experts

 

PCI-SIG, PCI Express and PCIe are registered trademarks of PCI-SIG

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