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Key Features & Specifications

Automated stress calibration with test software N5990A-101

  • PCI Express 1.0a, 2.5 GT/s
  • PCI Express 1.1, 2.5 GT/s
  • PCI Express 2.0, 5.0 GT/s and 2.5 GT/s
  • PCI Express 3.0, 8.0 GT/s, 5.0 GT/s and 2.5 GT/s
  • PCI Express 4.0, 16 GT/s (beta version)
  • Supports PCI Express Base Specification as well as CEM form factor compliance testing and U.2 form factor compliance testing (8 GT/s only)
  • Compliance testing, including tests 2.8 and 2.9, as well as characterization measurements like transmit equalization coefficient matrix scan, jitter tolerance search and sensitivity tests
  • Optional link equalization test 2.3, 2.4, 2.7, 2.10 and 2.11, requires option N5990A-501

Highly integrated J-BERT M8020A for a clean test setup

  • Two data rate options M8041A-C16 covers PCI Express data rates up to 16 GT/s, M8041A-C08 if coverage up to 8 GT/s is sufficient
  • Built-in Pre- and post-cursor de-emphasis, option M8041A-0G4
  • All sinusoidal interference and jitter sources built-in, options M8041A-0G7 and M8041A-0G3
  • Adjustable intersymbol interference built into J-BERT M8020A’s output stage, option M8041A-0G5
  • Built-in Multiplying PLL for 100MHz reference clock with SSC (mother board test), option M8041A-0G6
  • Interactive link training for PCIe 8 GT/s and 16 GT/s, option M8041A-0S4 (8 GT/s and 16 GT/s) or option M8041A-0S1 (8 GT/s only)
  • Error counting in loopback mode while SKP Ordered Set length varies, option M8041A-0S2 


Accurate PCI Express Receiver Characterization

Until PCI Express 3.0 was released the PCI SIG did not deem RX testing to be required for PCI Express compliance workshops. Transmission rates of 8 GT/s and 16 GT/s cause significant challenges for the design and test of ASICs, chips and boards and receiver testing is normative now.
Keysight offers a test set for accurate characterization of PCI Express receiver ports for R&D and validation test. The test solution covers PCI Express 1.0a, 1.1, 2.0, 3.0 and 4.0 (beta). All transfer rates including 16 GT/s are supported. Next to ASIC testing according to the PCI Express Base Specification the test setup can be configured for CEM form factor and U.2 form factor testing (PCI Express 3.0 8 GT/s only).

What are the Key Challenges of PCI Express 3.0 and 4.0 Receiver Testing?

Transmitting 8 GT/s over traditional PC board traces causes significant signal degradations. The receiver test ensures that the receiver under test can detect bits properly (at a BER level of 10-12) at worst-case stress conditions. For PCI Express 3.0 receiver test a stressed voltage eye and a stressed jitter eye test is defined by the base specification. The test challenges include optimizing transmit and receive equalization with 3 taps, emulating three different lengths of calibration channels, device link training with 128/130 bit coded pattern sequences, as well as specific periodic and random jitter conditions. However, the most challenging requirement is to implement the new procedure for calibrating PCI Express 3.0 & 4.0 compliant stress conditions as a receiver would see them after applied equalization. This procedure requires post-processing of signals captured at an accessible test point.
The stress signal for 16 GT/s is adjusted by varying ISI, SJ and DM-SI rather than varying launch amplitude, RJ and DM-SI for the 8 GT/s stress signal. Another important change is that a mated CEM connector is now required to be part of the base specification test channel for 16 GT/s receiver testing. While this mated CEM connector has to reside on channel boards, the adjustable ISI element can be implemented either by a selection of ISI traces of different length or more conveniently by using the adjustable ISI option of the J-BERT M8020A data output stages.
The stressed voltage and stressed jitter tests are combined into just one receiver test at 16 GT/s.

PCI Express 4.0 Base Specification Receiver Test Set J-BERT

PCI Express 4.0 Base Specification Receiver Test Setup


What are the Key Challenges of PCI Express Link Equalization Testing?

Link equalization testing verifies if the procedures for optimizing the link between receiver and the link partner’s transmitter. The test instrument needs to act as a link partner and perform the required protocol handshakes sufficiently fast.
Receiver link equalization testing is very similar to normal receiver testing. The test is performed with the stress signal applied using the receiver test setup. The difference is that the device under test is trained into loopback through L0 and recovery. Phases 0 through 3 are performed. The device under test is setting the test instrument’s preshoot and de-emphasis during the respective phase. The training is considered successful if the device under test’s receiver is able to achieve the required bit error rate.
Transmitter equalization testing verifies if the device under test is answering to the requested transmitter changes correctly, tests 2.3, 2.4 and 2.7, as well as in the correct amount of time in case of tests 2.4 and 2.7. The BERT is sending transmit equalization requests and trains the device under test into loopback. The device under test's signal is analyzed using an oscilloscope. To be able to verify the response times of a device under test it is essential that the BERT is providing a trigger signal to the oscilloscope to enable capturing of the handshake between BERT and device under test at the time of the sent transmit equalization change request.

PCI Express 3.0 Link Equalization Test 2.4 J-BERT M8020A

PCI Express Transmitter Link Equalization Test of an Add In Card


What does Keysight offer?

Keysight's complete and accurate receiver test solution is based on the J-BERT M8020A high-performance BERT, an Infiniium 90000 Series high-performance oscilloscope with at least 25 GHz bandwidth and the N5990A test automation software. To increase test efficiency switch matrixes for RX as well TX testing and remote programmable power strips are supported optionally.

PCI Express RX Test J-BERT M8020A optional switch matrix

PCI Express RX Test Station Configuration


Keysight supports RX and link equalization testing of ASICs (according to the base specification), CEM add-in cards and CEM motherboards as well as U.2 devices and hosts (according to the PCI Express Architecture PHY Test Specification).

PCI Express RX and Link EQ Test Report J-BERT M8020A

Results can be reported as Excel workbook or as HTML report. Optionally results can be collected in a database.

Recommended Instrument Configuration for Keysight PCI Express Receiver Test Setup

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PCI-SIG, PCI Express and PCIe are registered trademarks of PCI-SIG

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