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M8020A J-BERT High-Performance BERT Configuration for Bench-Top 5-Slot Chassis

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Prices for: United States

* Prices are subject to change without notice. Prices shown are Manufacturer's Suggested Retail Prices (MSRP). Prices shown are exclusive of taxes.

Key Features & Specifications

  • Data rates up to 8.5/ 16 Gb/s for pattern generator and error detector
  • 1- 4 16 Gb/s BERT channels in a 5-slot AXIe chassis
  • Integrated and calibrated jitter injection: RJ, PJ1, PJ2, SJ, BUJ, sinusoidal interference(common-mode and differential-mode), SSC (triangular and arbitrary, residual)
  • 8- tap de-emphasis (positive and negative) up to 20 dB
  • Interactive link training for PCI Express
  • Built-in clock data recovery and equalization
  • Modules and options are upgradeable
  • Extension to 32 Gb/s possible with M8061A multiplexer

Description

The high-performance Keysight J-BERT M8020A enables fast, accurate receiver characterization of single- and multi-lane devices running up to 16 or 32 Gb/s.

With today’s highest level of integration, the M8020A streamlines your test setup. In addition, automated in situ calibration of signal conditions ensures accurate and repeatable measurements. And, through interactive link training, it can behave like your DUT’s link partner. All in all, the J-BERT M8020A will accelerate insight into your design.

Target applications

R&D and test engineers who characterize, verify compliance of chips, devices, boards and systems with serial I/O ports up to 16 Gb/s and 32 Gb/s. The M8020A can be used to test popular serial bus standards, such as: PCI Express®, USB, MIPI M-PHYTM, SATA/SAS, DisplayPort, SD UHS-II, Fibre Channel, QPI, memory buses, backplanes, repeaters, active optical cables, Thunderbolt, 10 GbE, 100GbE (optical and electrical), SFP+, CFP2/4 transceivers, CEI.

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