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Key Features & Specifications

  • Data is decoded and displayed at any level of detail from the protocol to binary
  • The protocol-decode software executes in the logic analyzer and takes user input on system attributes (Burst length, CAS and Additive Latency, Chip Selects) to decode the key LPDDR or LPDDR2 bus signals
  • Present a display that lists the transaction type, address, data and command condition


B4623A bus decoder for LPDDR and LPDDR2 validation provides complete protocol decode of memory transactions using a Keysight logic analyzer as the analysis execution engine. The B4623A protocol-decode software translates acquired signals into easily understood bus transactions, at the full bus speed.